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w WM8948 stereo low-power codec with video buffer and touch panel controller wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, may 2011, rev 4.1 copyright ? 2011 wolfson microelectronics plc description the WM8948 is a highly integrated low power hi-fi codec designed for portable devices such as digital still cameras. up to 6 analogue inputs may be connected; a 2-channel digital microphone interface is also provided. flexible output mixing options support single-ended and differential configurations, with outputs derived from the digital audio paths or from analogue bypass paths. twin stereo outputs or stereo line and mono btl headphone/speaker drive may be supported. flexible digital mixing and powerful dsp functions are available. programmable filters and other processes may be applied to the adc or dac signal paths. the dsp functions include 3d- stereo enhancement, 5 notch filters, 5-band eq, dynamic range control and the wolfson retune? feature. the retune? feature is a sophisticated digital filter that can compensate for imperfect characteristics of the housing, loudspeaker or microphone components in an application. the retune? algorithm can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. the WM8948 is controlled via a i2c or spi interface. additional functions include 4-wire touch panel controller, auxiliary adc, digital beep generator, video buffer, programmable gpio functions, frequency locked loop (fll) for flexible clocking support and integrated ldo for low noise supply regulation. the WM8948 is supplied in 36-ball w-csp package, ideal for portable systems. features ? hi-fi audio codec - 94db snr during adc recording (?a? weighted) - 96db snr during dac playback (?a? weighted) ? 6 analogue audio inputs ? integrated bias reference for electret microphones ? 2-channel digital microphone interface ? powerful digital mixing / dsp functions: - 3d-stereo enhancement - 5-notch filters - 5-band equalizer (eq) - retune? parametric filter - dynamic range control and noise gate - low-pass/high-pass filters - direct form 1 (df1) programmable digital filter ? digital beep generator ? 4 analogue audio outputs ? stereo line output ? mono btl headphone/speaker output driver ? i2s digital audio interface - sample rates 8khz to 48khz ? frequency locked loop (fll) frequency conversion / filter ? video buffer function ? 4-wire touch panel interface controller ? auxiliary adc for dc measurement or battery monitoring ? integrated ldo low-noise voltage regulator ? 36-ball w-csp package (2.96 x 3.06 x 0.7mm, 0.5mm pitch) applications ? digital still cameras (dsc) ? multimedia phones
WM8948 production data w pd, may 2011, rev 4.1 2 table of contents description ....................................................................................................... 1 features............................................................................................................. 1 applications ..................................................................................................... 1 table of contents ......................................................................................... 2 block diagram ................................................................................................. 5 pin configuration ........................................................................................... 6 ordering information .................................................................................. 6 pin description ................................................................................................ 7 absolute maximum ratings ......................................................................... 8 recommended operating conditions ..................................................... 8 thermal performance ................................................................................. 9 electrical characteristics .................................................................... 10 terminology ........................................................................................................... 14 typical performance .......................................................................................... 15 power consumption ............................................................................................ 16 audio signal paths diagram ..................................................................... 17 signal timing requirements ..................................................................... 18 system clock timing ............................................................................................ 18 audio interface timing ....................................................................................... 18 master mode ................................................................................................................... ..................... 18 slave mode .................................................................................................................... ....................... 19 control interface timing ................................................................................. 20 device description ....................................................................................... 23 introduction .......................................................................................................... 23 analogue input signal path ............................................................................. 24 input pga enable .............................................................................................................. .................. 25 input pga configuration ....................................................................................................... ......... 25 microphone bias control ....................................................................................................... ....... 26 input pga gain control ........................................................................................................ ........... 26 digital microphone interface ......................................................................... 29 analogue-to-digital converter (adc) .......................................................... 30 adc volume control ............................................................................................................ ............ 31 adc high pass filter .......................................................................................................... ............... 33 dsp core .................................................................................................................. 34 dsp configuration modes ....................................................................................................... ....... 34 low-pass / high-pass filter (lpf/hpf) ......................................................................................... 35 3d surround ................................................................................................................... ..................... 36 5-notch filter ................................................................................................................ ..................... 36 df1 filter .................................................................................................................... .......................... 37 retune tm filter ....................................................................................................................... ............ 38 5-band eq ..................................................................................................................... .......................... 38 dynamic range control (drc) ................................................................................................... .... 39 signal enhancement register controls ................................................................................. 39 dynamic range control (drc) .......................................................................... 41 drc compression / expansion / limiting ..................................................................................... 41 gain limits ................................................................................................................... .......................... 44 gain readback ................................................................................................................. .................... 45 dynamic characteristics ....................................................................................................... ........ 45 anti-clip control ............................................................................................................. .................. 47 quick-release control ......................................................................................................... .......... 47 drc initial value ............................................................................................................. .................... 48
production data WM8948 w pd, may 2011, rev 4.1 3 digital-to-analogue converter (dac) .......................................................... 48 dac digital volume control .......................................................................................................... 48 dac auto-mute ................................................................................................................. .................... 51 dac sloping stopband filter ................................................................................................... ..... 51 digital beep generator ..................................................................................... 52 output signal path .............................................................................................. 53 output signal paths enable .................................................................................................... ...... 54 line output mixer control ..................................................................................................... ....... 55 speaker pga mixer control ..................................................................................................... ..... 57 speaker pga volume control ....................................................................................................... 60 speaker output control ................................................................................................................ 62 analogue outputs ............................................................................................... 63 line outputs .................................................................................................................. ...................... 63 speaker outputs ............................................................................................................................... . 63 external components for line output .................................................................................... 63 ldo regulator ...................................................................................................... 63 reference voltages and master bias .......................................................... 66 pop suppression control................................................................................. 68 disabled output control ....................................................................................................... ........ 68 output discharge control ...................................................................................................... ..... 69 digital audio interface ...................................................................................... 70 master and slave mode operation ............................................................................................. 7 0 audio data formats ............................................................................................................ .............. 71 companding .................................................................................................................... ...................... 74 loopback ...................................................................................................................... ......................... 76 digital pull-up and pull-down ................................................................................................. .... 77 clocking and sample rates .............................................................................. 78 digital mic clocking .......................................................................................................... ............... 80 frequency locked loop (fll) ................................................................................................... ..... 81 example fll calculation ....................................................................................................... ......... 84 example fll settings .......................................................................................................... .............. 85 video buffer ........................................................................................................... 86 recommended video buffer initialisation sequence .......................................................... 88 auxiliary adc .......................................................................................................... 90 auxadc control ................................................................................................................ ................. 90 auxadc input configuration .................................................................................................... ..... 91 auxadc readback ............................................................................................................... ................ 92 touch panel controller .... .............................................................................. 93 touch panel control ........................................................................................................... ............ 93 touch panel readback .......................................................................................................... .......... 94 touch panel operating principles ............................................................................................. 95 general purpose input/output ...................................................................... 97 gpio function select .......................................................................................................... ........... 100 interrupts ............................................................................................................ 101 control interface ............................................................................................ 103 selection of control interface mode ................................................................................... 104 2-wire (i2c) control mode ..................................................................................................... ........ 104 3-wire (spi) control mode...................................................................................................... ....... 107 4-wire (spi) control mode...................................................................................................... ....... 107
WM8948 production data w pd, may 2011, rev 4.1 4 power management ........................................................................................... 108 thermal shutdown ............................................................................................ 111 power on reset .................................................................................................. 111 recommended power up/down sequence ......................................... 113 software reset and device id ....................................................................... 115 register map ................................................................................................. 116 register bits by address ................................................................................ 122 digital filter characteristics ............................................................. 177 adc filter response .......................................................................................... 178 adc highpass filter response ...................................................................... 179 dac filter response .......................................................................................... 180 applications information ....................................................................... 182 recommended external components ......................................................... 182 audio input paths ............................................................................................................................. 1 82 headphone / line output paths ................................................................................................. . 182 btl speaker output connection................................................................................................ 1 83 power supply decoupling ....................................................................................................... .... 183 microphone bias circuit ....................................................................................................... ........ 184 video buffer components ............................................................................................................ 185 recommended external components diagram .................................................................... 186 pcb layout considerations ............................................................................ 186 package dimensions .................................................................................. 187 important notice ........................................................................................ 188 address: ................................................................................................................. 188 revision history .......................................................................................... 189
production data WM8948 w pd, may 2011, rev 4.1 5 block diagram in1r in2r pga_r - + aux2 aux1 bypass left bypass right -12db to +35.25db (step = 0.75db) spkpgar min = -57db max = +6db step = 1db in1l/dmicdat in2l pga_l - + -12db to +35.25db (step = 0.75db) adc r adc l aux1 aux2 adc / record digital filters dsp core (3d surround, re-tune eq, dynamic range control) dac digital filters dac r dac l mixspkr mixspkl mixoutr mixoutl spkpgal min = -57db max = +6db step = 1db + + spkoutl spkoutr lineoutl lineoutr control interface fll gpio sysclk digital audio interface 250k 250k 50k 50k 4k 5k adcref, dacref ldo xn yp yn xp digital mic interface touch panel interface aux adc -1 -1 + + + + spkoutl spkoutr digital beep generator dmicclk (gpio) dmicdat lpf clamp w WM8948 ldovdd inverted dacl dacl dacr inverted dacr aux2 aux1 bypass left inverted dacl dacl dacr inverted dacr aux2 aux1 bypass right inverted dacl dacl dacr inverted dacr aux2 aux1 bypass left inverted dacl dacl dacr inverted dacr aux2 aux1 bypass right aux1 aux1
WM8948 production data w pd, may 2011, rev 4.1 6 pin configuration the WM8948 is supplied in a 36-ball csp format. the pin configuration is illustrated below, showing the top-down view from above the chip. sda bclk in2l aux1 cs/ gpio2 lineoutl in1r vbin aux2 in1l/ dmicdat in2r vbrefr micbias vmidc ldovout spkvdd xp yn gnd ldovdd spkoutl sclk sdout/ gpio4 dacdat lrclk dbvdd cifmode /gpio3 gpio1 dcvdd yp xn adcdat spkoutr lineoutr vbout mclk 16 5 4 3 2 a f e d c b ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8948ecs/r -40 c to +85 c 36-ball w-csp (pb-free, tape and reel) msl1 260 o c note: reel quantity = 3500
production data WM8948 w pd, may 2011, rev 4.1 7 pin description pin no name type description a1 spkvdd supply supply for speaker driver a2 ldovout supply ldo output a3 ldovdd supply ldo supply input a4 vmidc analogue output midrail voltage decoupling capacitor a5 yn analogue input / output touch panel (bottom) connection a6 xp analogue input / output touch panel (right) connection b1 spkoutr analogue output right speaker mixer output b2 spkoutl analogue output left speaker mixer output b3 gnd supply ground b4 xn analogue input / output touch panel (left) connection b5 yp analogue input / output touch panel (top) connection b6 aux1 analogue input aux input (audio or auxadc input) c1 lineoutl analogue output left line mixer output c2 lineoutr analogue output right line mixer output c3 adcdat digital output adc / digital microphone digital audio data c4 micbias analogue output microphone bias c5 aux2 analogue input aux input (audio or auxadc input) c6 in2l analogue input left input 2 d1 vbrefr analogue output video buffer current reference resistor connection d2 vbout analogue output video buffer output d3 cs /gpio2 digital input / output chip select / gpio2 d4 in1l/dmicdat analogue input / digital input left input 1 / digital microphone data input d5 in1r analogue input right input 1 d6 in2r analogue input right input 2 e1 vbin analogue input video buffer input e2 bclk digital input / output audio interface bit clock e3 lrclk digital input / output audio interface left / right clock e4 sdout/gpio4 digital input / output control interface data output / gpio4 e5 dcvdd supply digital core supply e6 sda digital input / output control interface data input / output f1 mclk digital input master clock f2 dacdat digital input dac digital audio data f3 gpio1 digital input / output gpio1 f4 cifmode/gpio3 digital input / output control interface mode select / gpio3 f5 dbvdd supply digital buffer (i/o) supply f6 sclk digital input control interface clock input
WM8948 production data w pd, may 2011, rev 4.1 8 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages (dcvdd) -0.3v 2.5v supply voltages (ldovdd, dbvdd, spkvdd) -0.3v 4.5v voltage range digital inputs -0.7v dbvdd +0.7v voltage range analogue inputs -0.7v ldovdd +0.7v operating temperature range, t a -40oc +85oc junction temperature, t jmax -40oc +150oc storage temperature after soldering -65oc +150oc recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.62 1.8 1.98 v digital supply range (i/o) dbvdd 1.71 3.3 3.6 v analogue supply ldovdd 2.4 3.3 3.6 v speaker supply range spkvdd 1.71 3.3 3.6 v ground gnd 0 v note: to ensure pop-free device start-up, ldovdd must be enabled before spkvdd
production data WM8948 w pd, may 2011, rev 4.1 9 thermal performance thermal analysis should be performed in the intended application to prevent the WM8948 from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd balls through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air as illustrated below in figure 1: - package top to air (radiation). - package bottom to pcb (radiation). - package balls to pcb (conduction). figure 1 heat transfer paths the temperature rise t r is given by t r = p d * ? ja - p d is the power dissipated in the device. - ? ja is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ? ja is determined with reference to jedec standard jesd51-9. the junction temperature t j is given by t j = t a +t r , where t a is the ambient temperature. parameter symbol min typ max unit operating temperature range t a -40 85 c operating junction temperature t j -40 125 c thermal resistance (junction to case) ? jc 30 c/w thermal resistance (junction to ambient) ? ja 60 c/w notes: 1. junction temperature is a function of ambient temperature and of the device operating conditions. the ambient temperature limits and junction temperature limits must both be observed.
WM8948 production data w pd, may 2011, rev 4.1 10 electrical characteristics test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue inputs (in1l, in2l, in1r, in2r) maximum input signal level (changes in proportion to ldovout) single-ended input 1.0 0 vrms dbv pseudo-differential input 0.7 -3.1 vrms dbv input resistance (in1l, in1r) +35.25db gain 3.5 k 0db gain 104 k -12db gain 166 k input resistance (in2l, in2r) all gain settings 96 k input capacitance 10 pf analogue inputs (aux1, aux2) maximum input signal level (changes in proportion to ldovout) aux1 or aux2 enabled as audio input 1.0 0 vrms dbv input resistance input mixer path (0db) 100 k output mixer / direct speaker path (0db) 15 k output mixer / direct speaker path (-6db) 30 k input capacitance 10 pf analogue inputs programmable gain amplifiers (pgas) minimum programmable gain -12 db maximum programmable gain 35.25 db gain step size guaranteed monotonic 0.75 db mute attenuation 92 db common mode rejection ratio 1khz input 110 db speaker output programmable gain amplifiers (pgas) minimum programmable gain -57 db maximum programmable gain 6 db gain step size guaranteed monotonic 1 db mute attenuation 71 db adc input path performance (input pgas to adc) snr (a-weighted) 84 94 db thd -1dbfs input -83 -75 db thd+n -1dbfs input -77 -70 db channel separation (left/right) 95 db psrr (with respect to ldovdd) 217hz 1khz 77 90 db
production data WM8948 w pd, may 2011, rev 4.1 11 parameter symbol test conditions min typ max unit bypass to line output (single-ended in2l, in2r to input pga to line output, 10k / 50pf) snr (a-weighted) pga gain = 0db inppgavol = 0db 90 98 db thd+n pga gain = 0db inppgavol = 0db -89.5 -82 db bypass to speaker output (single-ended aux1, aux2 to input pga to spkmix to speaker output, 10k / 50pf) snr (a-weighted) pga gain = 0db inppgavol = 0db 90 96 db thd+n pga gain = 0db inppgavol = 0db -86.5 -77 db dac output path performance (dac to line output, 10k / 50pf) maximum output signal level (changes in proportion to ldovout) 1 vrms snr (a-weighted) 85 96 db thd -78 -72 db thd+n -76 -70 db channel separation (left/right) 90 db mute attenuation 125 db psrr (with respect to ldovdd) 217hz 1khz 48 60 db line output resistance 10 k line output capacitance 50 pf dac output path performance (dac to speaker output, 10k / 50pf) maximum output signal level (changes in proportion to ldovout) 1 vrms snr (a-weighted) 96 db thd -78 db thd+n -76 db speaker output performance (speaker output, 8 btl) snr (a-weighted) 90 96 db thd p o =150mw 0.03 -68 % db p o =350mw 2.944 -30.6 % db thd+n p o =150mw 0.05 -66 % db p o =350mw 3.72 -28.6 % db channel separation (left/right) 90 db mute attenuation 92 db psrr (with respect to ldovdd) 217hz 1khz 48 60 db psrr (with respect to spkvdd) 217hz 1khz 89 79 db speaker resistance 8 speaker capacitance 50 pf
WM8948 production data w pd, may 2011, rev 4.1 12 parameter symbol test conditions min typ max unit auxadc & touch panel interface maximum input signal level (changes in proportion to ldovdd) 3.3 v input leakage current aux pin not selected as auxadc input 10 na input resistance 50 input capacitance 10 pf auxadc resolution 12 bits auxadc conversion time 20.8 s auxadc accuracy 6 lsb touch panel switch matrix resistance 20 maximum pen-down detection sensitivity pull- up resistor 55 63 70 k touch pressure current source tch_isel = 0 230 ua tch_isel = 1 460 ua pen-down detection threshold (changes in proportion to ldovdd) 1.65 v digital inputs/outputs input high level 0.7 dbvdd v input low level 0.3 dbvdd v output high level i ol = 1ma 0.8 dbvdd v output low level i oh = -1ma 0.2 dbvdd v input capacitance 10 pf input leakage all digital pins except cifmode -900 900 na cifmode pin -90 90 na ldo regulator input voltage ldovdd 2.4 3.3 3.6 v output voltage ldovout ldo_ref_sel = 0 3.0 v maximum output current (see note) 50 ma output voltage accuracy i load = 50ma 2 % quiescent current no load 55 a leakage current 1 a psrr (with respect to ldovdd) 217hz 1khz 40 49 db
production data WM8948 w pd, may 2011, rev 4.1 13 parameter symbol test conditions min typ max unit video buffer maximum output voltage swing vom f=100khz, thd=1% 1.10 1.25 1.50 v pk-pk voltage gain av vb_gain = 1, r ref =187 , r load =75 , r source =75 5.08 6 7.94 db vb_gain = 0, r ref =187 , r load =75 , r source =75 -0.92 0 1.94 db gain step size 6 db differential gain dg vin = 1v pk-pk -2.0 0.3 +2.0 % differential phase dp vin = 1v pk-pk -2.0 0.7 +2.0 deg snr vsnr 40 60 100 db sync tip offset above gnd vb_pd = 0 vb_gain = 1 0 40 75 mv third order low pass filter response (referenced to 100khz) r ref =187 , r load =75 , r source =75 , 0db gain 2.4mhz -0.5 0 0.5 db 5.13mhz -0.5 -0.2 0.5 db 9.04mhz -3.0 -1.6 0 db 13.32mhz -11.0 -7.0 -3.0 db psrr (with respect to ldovout) 100khz 60 db clocking mclk frequency 30hz 27mhz hz fll output frequency 2.045 50 mhz fll lock time 2 ms micbias bias voltage (changes in proportion to ldovout) micbias micb_lvl = 0 2.7 v micb_lvl = 1 1.95 v bias current source 3 ma output noise spectral density 1khz to 20khz 15 nv/ hz psrr (with respect to ldovdd) 217hz 1khz 70 85 db analogue reference levels midrail reference voltage (changes in proportion to ldovout) vmid vmid_ref_sel = 1 vmid_ctrl=1 1.5 v bandgap reference bg_vsel=01010 -10% 1.5 +10% v note: the maximum ldo output current is the total internal and external load capability; internal circuits of the WM8948 will typical ly account for 25ma of this capacity.
WM8948 production data w pd, may 2011, rev 4.1 14 terminology 1. signal-to-noise ratio (db) ? snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20hz to 20khz. this ratio is also called idle channel noise. (no auto-zero or mute function is employed). 2. total harmonic distortion (db) ? thd is the difference in level between a 1khz reference sine wave output signal and the first seven harmonics of the output signal. the amplitude of the fundamental frequency of the output signal is compared to the rms value of the next seven harmonics and expressed as a ratio. 3. total harmonic distortion plus noise (db) ? thd+n is the difference in level between a 1khz reference sine wave output signal and all noise and distortion products in the audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms value of all other noise and distortion products and expressed as a ratio. 4. channel separation (l/r) (db) ? is a measure of the coupling between left and right channels. a full scale signal is applied to the left channel only, and the right channel amplitude is measured. next, a full scale signal is applied to the right channel only, and the left channel amplitude is measured. the worst case channel separation is quoted; this is the difference in level between the full-scale output and the cross-channel output signal level, expressed as a ratio. 5. mute attenuation ? this is a measure of the difference in level between the full scale output signal and the output with mute applied. 6. power supply rejection ratio (db) ? psrr is a measure of ripple attenuation between a power supply rail and a signal output path. with the signal path idle, a small sine wave ripple is applied to power supply rail. the amplitude of the supply ripple is compared to the amplitude of the output signal generated and is expressed as a ratio. 7. all performance measurements are carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out-of-band noise; although it is not audible, it may affect dynamic specification values.
production data WM8948 w pd, may 2011, rev 4.1 15 typical performance WM8948 adc - thd+n v ampltiude - adc - slave mode -120 -50 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 d b f s -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbv WM8948 dac - thd+n v ampltiude - dac to lineout 10kohm -120 -40 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b v -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs WM8948 - dac to spkout 8ohm btl thd+n v amplitude - 48khz -120 -10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 d b v -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs t
WM8948 production data w pd, may 2011, rev 4.1 16 power consumption typical power consumption dcvdd dbvdd ldovdd spkvdd total total condition 1.8 3.3 3.3 3.3 current (ma) power (mw) powerdown (no data) 0.178 0.062 0.007 0.002 0.267 0.555 powerdown (+master bias) 0.178 0.062 0.021 0.002 0.282 0.603 powerdown (+master bias+vmid buffer) 0.178 0.062 0.142 0.002 0.403 1.001 powerdown (+master bias+vmid buffer+vmid) 0.178 0.063 1.092 0.002 1.353 4.137 playback to lineout (no data) 4.272 0.057 2.336 0.007 6.672 15.609 playback to lineout (with data) 4.293 0.062 2.356 0.007 6.718 15.728 video buffer only 0.178 0.062 5.088 0.020 5.348 17.380 touch panel onl y 0.223 0.062 0.257 0.007 0.549 1.477 playback to speaker (no data) 4.272 0.057 2.877 4.707 11.647 32.904 playback to speaker (with data) 4.294 0.062 2.895 4.730 11.696 33.095 playback to speaker (with data) 32ohm 4.295 0.062 2.895 5.790 13.042 36.595 playback to speaker (with data) 16ohm 4.295 0.062 2.896 6.275 13.528 38.199 mono record (nodata) 2.992 0.088 3.728 0.007 6.815 18.001 mono record (with data) 2.999 0.100 3.727 0.007 6.833 18.049 stereo record (no data) 4.652 0.128 6.692 0.007 11.479 30.903 stereo record (with data) 4.654 0.128 6.692 0.007 11.481 30.907 playback and record (no data) 5.673 0.120 10.054 4.408 20.255 58.333 a ll on 5.408 0.099 62.323 4.211 72.041 229.622
production data WM8948 w pd, may 2011, rev 4.1 17 audio signal paths diagram
WM8948 production data w pd, may 2011, rev 4.1 18 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 2 master clock timing test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c. parameter symbol conditions min typ max unit master clock timing mclk cycle time t mclky 0.037 s s mclk duty cycle (= t mclkh : t mclkl ) 60:40 40:60 audio interface timing master mode figure 3 audio interface timing - master mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit audio interface timing - master mode lrclk propagation delay from bclk falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns dacdat setup time to bclk rising edge t dst 20 ns dacdat hold time from bclk rising edge t dht 10 ns
production data WM8948 w pd, may 2011, rev 4.1 19 slave mode figure 4 audio interface timing ? slave mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit audio interface timing - slave mode bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set-up time to bclk rising edge t lrsu 20 ns lrclk hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns dacdat set-up time to bclk rising edge t ds 20 ns note: bclk period must always be greater than or equal to mclk period.
WM8948 production data w pd, may 2011, rev 4.1 20 control interface timing sclk (input) sda t 4 t 3 start t 8 stop t 5 t 2 t 1 t 9 t 7 t 6 figure 5 control interface timing - 2-wire (i2c) control mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit sclk frequency 400 khz sclk low pulse-width t 1 1300 ns sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sda, sclk rise time t 6 300 ns sda, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
production data WM8948 w pd, may 2011, rev 4.1 21 cs (input) sclk (input) sda (input) t csu t cho t sch t scl t scy t dho t dsu figure 6 control interface timing - 3-wire (spi) control mode (write cycle) note: the data is latched on the 32 nd falling edge of sclk after 32 bits have been clocked into the device sclk (input) sda (output) t dl cs (input) figure 7 control interface timing - 3-wire (spi) control mode (read cycle) test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit cs falling edge to sclk rising edge t csu 40 ns sclk falling edge to cs rising edge t cho 10 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sda to sclk set-up time t dsu 40 ns sda to sclk hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sda output transition t dl 40 ns
WM8948 production data w pd, may 2011, rev 4.1 22 figure 8 control interface timing - 4-wire (spi) control mode (write cycle) note: the data is latched on the 32 nd falling edge of sclk after 32 bits have been clocked into the device figure 9 control interface timing - 4-wire (spi) control mode (read cycle) test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit cs falling edge to sclk rising edge t csu 40 ns sclk falling edge to cs rising edge t cho 10 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sda to sclk set-up time t dsu 40 ns sda to sclk hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sdout transition t dl 40 ns
production data WM8948 w pd, may 2011, rev 4.1 23 device description introduction the WM8948 is a highly integrated low power hi-fi codec designed for portable devices such as digital still cameras and multimedia phones. flexible analogue interfaces and powerful digital signal processing (dsp) in a 2.96 x 3.06mm footprint make it ideal for small portable devices. the WM8948 supports up to 6 analogue audio inputs. one pair of single-ended or pseudo differential microphone / line inputs is selected as the adc input source. the two auxiliary inputs can be selected as line inputs to the adc, or as direct signal paths to the output mixers. an integrated bias reference is provided to power standard electret microphones. a two-channel digital microphone interface is also supported, with direct input to the dsp core via the adcs. the stereo hi-fi adcs and dacs operate at sample rates from 8khz up to 48khz. a high pass filter is available in the adc path for removing dc offsets and suppressing low frequency noise such as mechanical vibration and wind noise. a digital tone (?beep?) generator allows audio tones to be injected into the dac output path. the WM8948 provides a powerful dsp capability for configurable filtering and processing of the digital audio paths. the dsp provides low-pass / high-pass filtering, 3d stereo enhancement, notch filters, 5-band eq, dynamic range control and a programmable df1 digital filter. the tuned notch filters allow narrow frequency bands to be attenuated, to provide filtering of motor noise or other unwanted sounds; the 5-band eq allows the signal to be adjusted for user-preferences. the dynamic range control provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. the df1 filter allows user-specified algorithms to be implemented in the digital signal chain. the wolfson retune? feature is a highly-configurable dsp algorithm which can be tailored to cancel or compensate for imperfect characteristics of the housing, loudspeaker or microphone components in the target application. the retune? algorithm coefficients and register contents are calculated using wolfson?s wisce? software; lab bench tests and audio reference measurements must be performed in order to determine the optimum settings. the digital signal routing between the adcs, dacs and i2s digital audio interface can be configured in different ways according to the application requirements. the dsp functions may be applied to the adc record path, or the dac playback path. four analogue output mixers are provided, connected to 4 analogue output pins. twin stereo outputs or stereo line and mono btl headphone/speaker may be connected to these outputs. the WM8948 incorporates an ldo regulator for compatibility with a wide range of supply rails; the internal ldo can also reduce any interference resulting from a noisy supply rail. the ldo regulator can also be used to provide a regulated supply voltage to other circuits. i2c or spi control interface modes for read/write access to the register map. a single external clock provides timing reference for all the digital functions; an integrated frequency locked loop (fll) also provides flexibility to perform frequency conversions and to remove noise/jitter from the external clock. the fll can be configured for reduced power consumption, or for different filtering requirements of the reference source. additional functions include a 4-wire controller for interface to standard resistive touch panels, a 12- bit auxiliary adc for dc measurement / battery monitoring, and also a current-mode video buffer providing excellent video signal reproduction at low operating voltages. up to 4 gpio pins may be configured for miscellaneous input/output, or for status indications from the touch panel, auxadc or temperature monitoring functions.
WM8948 production data w pd, may 2011, rev 4.1 24 analogue input signal path the WM8948 has six analogue input pins, which may be selected in many different configurations. the analogue input paths can support line and microphone inputs, in single-ended or pseudo- differential modes. two of the input pins (aux1 and aux2) may be configured either as audio inputs or may be used as inputs to the auxiliary adc for analogue measurement or monitoring. the left and right input pga audio channels are routed to the analogue to digital converters (adcs). there is also a bypass path for each channel, enabling the signal to be routed directly to the output mixers. the WM8948 input signal paths and control registers are illustrated in figure 10. figure 10 input signal paths
production data WM8948 w pd, may 2011, rev 4.1 25 input pga enable the input pgas (programmable gain amplifiers) are enabled using register bits inppgar_ena and inppgal_ena, as described in table 1. register address bit label default description r2 (02h) power management 1 13 inppgar_ena 0 right input pga enable 0 = disabled 1 = enabled 12 inppgal_ena 0 left input pga enable 0 = disabled 1 = enabled table 1 input pga enable to enable the input pgas, the reference voltage vmid and the bias current must also be enabled. see ?reference voltages and master bias? for details of the associated controls vmid_sel and bias_ena. input pga configuration microphone and line level audio inputs can be connected to the WM8948 in single-ended or differential configurations. (these two configurations are illustrated in figure 62 and figure 63 in the section describing the external components requirements - see ?applications information?.) for single-ended microphone inputs, the microphone signal is connected to the non-inverting input of the pgas, whilst the inverting inputs of the pgas are connected to vmid. for differential microphone inputs, the non-inverted microphone signal is connected to the non-inverting input of the pgas, whilst the inverted (or ?noisy ground?) signal is connected to the inverting input pins. line level inputs are connected in the same way as a single-ended microphone signal. the non-inverting input of the pgas is configured using the p_pgar_sel and p_pgal_sel registers. these registers allow the selection of three possible input pins to the associated pga. when the aux1 or aux2 pin is used as an audio input, that pin must be configured for audio using the aux1_audio or aux2_audio register bits. the inverting input of the pgas is configured using micrn_to_n_pgar and micln_to_n_pgal. these registers allow the pga to operate in either single-ended or pseudo-differential configuration. the registers for configuring the input pgas are described in table 2. register address bit label default description r39 (27h) input ctrl 8 aux2_audio 0 aux2 pin configuration 0 = non-audio signal 1 = ac-coupled audio signal 7 aux1_audio 0 aux1 pin configuration 0 = non-audio signal 1 = ac-coupled audio signal 5 micrn_to_n_ pgar 1 right input pga inverting input select 0 = connected to vmid 1 = connected to in2r 4 micln_to_n_ pgal 1 left input pga inverting input select 0 = connected to vmid 1 = connected to in2l
WM8948 production data w pd, may 2011, rev 4.1 26 register address bit label default description 3:2 p_pgar_sel [1:0] 01 right input pga non-inverting input select 00 = connected to in2r 01 = connected to in1r 10 = connected to aux2 11 = reserved 1:0 p_pgal_sel [1:0] 01 left input pga non-inverting input select 00 = connected to in2l 01 = connected to in1l 10 = connected to aux1 11 = reserved table 2 input pga configuration microphone bias control the WM8948 provides a low noise reference voltage suitable for biasing electret condenser (ecm) type microphones via an external resistor. refer to the ?applications information? section for recommended components. the micbias voltage is enabled using the micb_ena register bit; the voltage can be selected using the micb_lvl bit, as described in table 3. register address bit label default description r2 (02h) power management 1 4 micb_ena 0 microphone bias enable 0 = disabled 1 = enabled r39 (27h) input ctrl 6 micb_lvl 0 microphone bias voltage control 0 = 0.9 x ldovout 1 = 0.65 x ldovout table 3 microphone bias control input pga gain control the volume control gain for the left and right channels can be independently adjusted using the pgal_vol and pgar_vol register fields as described in table 4. the gain range is -12db to +35.25db in 0.75db steps. the gains on the inverting and non-inverting inputs to the pgas are always equal. each input pga can be independently muted using the pga mute bits. to prevent "zipper noise", a zero-cross function is provided on the input pgas. when this feature is enabled, volume updates will not take place until a zero-crossing is detected. in the case of a long period without zero-crossings, a timeout function is provided. when the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. the timeout clock is enabled using toclk_ena. see ?clocking and sample rates? for the definition of this bit. note that the zero-cross function can be supported without toclk enabled, but the timeout function will not be provided in this case. the pga_vu bits control the loading of the input pga volume data. when pga_vu is set to 0, the pga volume data will be loaded into the respective control register, but will not actually change the gain setting. the left and right input pga volume settings are both updated when a 1 is written to pga_vu; this makes it possible to update the gain of the left and right signal paths simultaneously.
production data WM8948 w pd, may 2011, rev 4.1 27 the input pga volume control register fields are described in table 4. register address bit label default description r40 (28h) left inp pga gain ctrl 8 pga_vu 0 input pga volume update writing a 1 to this bit will cause the left and right input pga volumes to be updated simultaneously. 7 pgal_zc 0 left input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 pgal_mute 1 left input pga mute 0 = disable mute 1 = enable mute 5:0 pgal_vol [5:0] 01_0000 (0db) left input pga volume 00_0000 = -12db 00_0001 = -11.25db ? 01_0000 = 0db ... 11_1111 = +35.25 (see table 5 for volume range) r41 (29h) right inp pga gain ctrl 8 pga_vu 0 input pga volume update writing a 1 to this bit will cause the left and right input pga volumes to be updated simultaneously. 7 pgar_zc 0 right input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 pgar_mute 1 right input pga mute 0 = disable mute 1 = enable mute 5:0 pgar_vol [5:0] 01_0000 (0db) right input pga volume 00_0000 = -12db 00_0001 = -11.25db ? 01_0000 = 0db ... 11_1111 = +35.25 (see table 5 for volume range) table 4 input pga volume control
WM8948 production data w pd, may 2011, rev 4.1 28 pgal_vol[5:0], pgar_vol[5:0] volume (db) pgal_vol[5:0], pgar_vol[5:0] volume (db) 00_0000 -12 10_0000 12 00_0001 -11.25 10_0001 12.75 00_0010 -10.5 10_0010 13.5 00_0011 -9.75 10_0011 14.25 00_0100 -9 10_0100 15 00_0101 -8.25 10_0101 15.75 00_0110 -7.5 10_0110 16.5 00_0111 -6.75 10_0111 17.25 00_1000 -6 10_1000 18 00_1001 -5.25 10_1001 18.75 00_1010 -4.5 10_1010 19.5 00_1011 -3.75 10_1011 20.25 00_1100 -3 10_1100 21 00_1101 -2.25 10_1101 21.75 00_1110 -1.5 10_1110 22.5 00_1111 -0.75 10_1111 23.25 01_0000 0 11_0000 24 01_0001 0.75 11_0001 24.75 01_0010 1.5 11_0010 25.5 01_0011 2.25 11_0011 26.25 01_0100 3 11_0100 27 01_0101 3.75 11_0101 27.75 01_0110 4.5 11_0110 28.5 01_0111 5.25 11_0111 29.25 01_1000 6 11_1000 30 01_1001 6.75 11_1001 30.75 01_1010 7.5 11_1010 31.5 01_1011 8.25 11_1011 32.25 01_1100 9 11_1100 33 01_1101 9.75 11_1101 33.75 01_1110 10.5 11_1110 34.5 01_1111 11.25 11_1111 35.25 table 5 input pga volume range
production data WM8948 w pd, may 2011, rev 4.1 29 digital microphone interface the WM8948 supports a two-channel digital microphone interface. the two-channel audio data is multiplexed on the in1l input pin and clocked using a gpio output. the analogue signal path from the in1l pin must be disabled when using the digital microphone interface; this is achieved by disabling the associated input pga, (ie. inppgal_ena= 0). the digital microphone input, dmicdat, is provided on the in1l/dmicdat pin. the associated clock, dmicclk, is provided on a gpio pin. the digital microphone input is selected as input by setting the dmic_ena bit. when the digital microphone input is selected, the adc input is deselected. the digital microphone interface configuration is illustrated in figure 11. note that the digital microphone may be powered from micbias or from ldovout; care must be taken to ensure that the respective digital logic levels of the microphone are compatible with the digital input thresholds of the WM8948. the digital input thresholds are referenced to dbvdd, as defined in ?electrical characteristics?. figure 11 digital microphone interface when any gpio pin is configured as dmicclk output, the WM8948 outputs a clock which supports digital mic operation at the adc sampling rate. the adc and record path filters must be enabled and the adc sampling rate must be set in order to ensure correct operation of all dsp functions associated with the digital microphone. volume control for the digital microphone interface signals is provided using the adc volume control. see ?analogue-to-digital converter (adc)? for details of the adc enable and volume control functions. see ?general purpose input / output? for details of configuring the dmicclk output. see ?clocking and sample rates? for the details of the sample rate control. when the dmic_ena bit is set, then the in1l pin is used as the digital microphone input dmicdat. up to two microphones can share this pin; the two microphones are interleaved as illustrated in figure 12. the digital microphone interface requires that mic1 (left channel) transmits a data bit each time that dmicclk is high, and mic2 (right channel) transmits when dmicclk is low. the WM8948 samples the digital microphone data in the middle of each dmicclk clock phase. each microphone must tri-state its data output when the other microphone is transmitting.
WM8948 production data w pd, may 2011, rev 4.1 30 figure 12 digital microphone interface timing the digital microphone interface control fields are described in table 6. register address bit label default description r2 (02h) power management 1 7 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0, the digital microphone clock (dmicclk) is held low. table 6 digital micr ophone interface control analogue-to-digital converter (adc) the WM8948 uses two 24-bit sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full-scale input level is proportional to ldovout. see ?electrical characteristics? section for further details. any input signal greater than full scale may overload the adc and cause distortion. the adcs and associated digital record filters are enabled by the adcl_ena and adcr_ena register bits. register address bit label default description r2 (02h) power management 1 11 adcr_ena 0 right adc enable 0 = disabled 1 = enabled adcr_ena must be set to 1 when processing right channel data from the adc or digital microphone. 10 adcl_ena 0 left adc enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing left channel data from the adc or digital microphone. table 7 adc enable control
production data WM8948 w pd, may 2011, rev 4.1 31 adc volume control the output of the adcs can be digitally amplified or attenuated over a range from -71.625db to +23.625db in 0.375db steps. the volume of each channel can be controlled separately using adcl_vol or adcr_vol. the adc volume is part of the adc digital filters block. the gain for a given eight-bit code x is given by: 0.375 (x-192) db for 1 x 255; mute for x = 0 the adc_vu bit controls the loading of digital volume control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously. the output of the adcs can be digitally muted using the adcl_mute or adcr_mute bits. both adcs are muted simultaneously when the adc_muteall bit is set. register address bit label default description r25 (19h) adc control 1 8 adc_muteall 0 adc digital mute for all channels 0 = disable mute 1 = enable mute on all channels r27 (1bh) left adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 8 adcl_mute 0 left adc digital mute 0 = disable mute 1 = enable mute 7:0 adcl_vol [7:0] 1100_0000 (0db) left adc digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db (see table 9 for volume range) r28 (1ch) right adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 8 adcr_mute 0 right adc digital mute 0 = disable mute 1 = enable mute 7:0 adcr_vol [7:0] 1100_0000 (0db) right adc digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db (see table 9 for volume range) table 8 adc digital volume control
WM8948 production data w pd, may 2011, rev 4.1 32 adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 18.000 31h -53.625 71h -29.625 b1h -5.625 f1h 18.375 32h -53.250 72h -29.250 b2h -5.250 f2h 18.750 33h -52.875 73h -28.875 b3h -4.875 f3h 19.125 34h -52.500 74h -28.500 b4h -4.500 f4h 19.500 35h -52.125 75h -28.125 b5h -4.125 f5h 19.875 36h -51.750 76h -27.750 b6h -3.750 f6h 20.250 37h -51.375 77h -27.375 b7h -3.375 f7h 20.625 38h -51.000 78h -27.000 b8h -3.000 f8h 21.000 39h -50.625 79h -26.625 b9h -2.625 f9h 21.375 3ah -50.250 7ah -26.250 bah -2.250 fah 21.750 3bh -49.875 7bh -25.875 bbh -1.875 fbh 22.125 3ch -49.500 7ch -25.500 bch -1.500 fch 22.500 3dh -49.125 7dh -25.125 bdh -1.125 fdh 22.875 3eh -48.750 7eh -24.750 beh -0.750 feh 23.250 3fh -48.375 7fh -24.375 bfh -0.375 ffh 23.625 table 9 adc digital volume range
production data WM8948 w pd, may 2011, rev 4.1 33 adc high pass filter a digital high-pass filter can be applied to the adc path to remove dc offsets. this filter can also be programmed to remove low frequency noise in handheld applications (e.g. wind noise, handling noise or mechanical vibration). this filter is controlled using the adc_hpf and adc_hpf_cut register bits (see table 10). note that the adc hpf is not enabled by default but must be used if drc_ena is enabled in register r29(1dh) bit 7. the drc will not function correctly unless this filter is enabled. when adc_hpf_cut=00, the high pass filter is optimised for hi-fi audio modes; the filter is designed to remove dc offsets without degrading the bass response and has a cut-off frequency of 3.7hz at fs=44.1khz. in the other adc_hpf_cut modes. the high pass filter is optimised for voice communication modes. it is recommended to select a cut-off frequency below 300hz; the preferred setting may vary according to the voice communication sample rate. (e.g. adc_hpf_cut=11 at fs=8khz or adc_hpf_cut=10 at fs=16khz). register address bit label default description r26 (1ah) adc control 2 2:1 adc_hpf_cut [1:0] 00 high pass filter configuration. 00 = 1st order hpf (fc=4hz at fs=48khz) 01 = 2nd order hpf (fc=122hz at fs=48khz) 10 = 2nd order hpf (fc=153hz at fs=48khz) 11 = 2nd order hpf (fc=196hz at fs=48khz) (see table 11 for cut-off frequencies at all supported sample rates) 0 adc_hpf 0 adc digital high pass filter enable 0 = disabled 1 = enabled table 10 adc high-pass filter control registers sample rate (khz) value of adc_hpf_cut bits 00 01 10 11 cut-off frequency (hz) 8.000 0.7 20 26 33 11.025 0.9 28 36 45 16.000 1.3 41 51 66 22.050 1.9 56 71 90 24.000 2.0 61 77 98 32.000 2.7 81 102 131 44.100 3.7 112 141 180 48.000 4.0 122 153 196 table 11 adc high-pass filter cut-off frequencies filter response plots for the adc high-pass filter are shown in ?digital filter characteristics?.
WM8948 production data w pd, may 2011, rev 4.1 34 dsp core dsp core is at the centre of the adc / dac / digital audio interface (i2s) blocks. it provides signal routing, and also implements a number of configurable signal processing functions. the signal processing functions are arranged in three blocks, as follows: ? signal enhancement 1 (se1) - low-pass / high-pass filter, 3d-stereo enhancement, 5 notch filters, generic ?direct-form 1? filter. ? signal enhancement 2 (se2) - retune? processing, 5-band equalizer. ? signal enhancement 3 (se3) - dynamic range control the dsp configuration modes and each of the signal enhancement blocks is described in the following sections. dsp configuration modes the dsp configuration mode is determined using the se_config register field; this configures the signal paths between the signal enhancement blocks and the adc / dac / i2s interfaces. the supported dsp modes are illustrated in figure 13. figure 13 dsp configuration modes
production data WM8948 w pd, may 2011, rev 4.1 35 record mode enables the entire set of signal enhancement functions in the adc path. the direct dac path is also active, without any signal enhancement functions; this allows basic audio playback and digital beep generation. playback mode enables the entire set of dsp functions in the dac path. the direct adc path is also active, without any dsp functions; this allows basic audio record functions to the host system. register address bit label default description r64 (40h) se config selection 3:0 se_config [3:0] 0000 dsp configuration mode select 0000 = record mode 0001 = playback mode 0010 = reserved 0011 = reserved table 12 dsp configuration mode select low-pass / high-pass filter (lpf/hpf) the low-pass / high-pass filter is part of the se1 block. this first-order filter can be configured to be high-pass or low-pass; it can also be bypassed. the cut-off frequency is programmable; the default setting is bypass (off). the left and right channel parameters may be programmed individually. the left and right filters are enabled using the se1_lhpf_l_ena and se1_lhpf_r_ena register bits defined in table 13. for the derivation of the other associated registers, refer to the configuration tools supplied with the WM8948 evaluation kit. example plots of the low-pass / high-pass filter response are shown in figure 14. 1klpf.res magnitude(db) 1khpf.res magnitude(db) 5klpf.res magnitude(db) 5khpf.res magnitude(db) 200lpf.res magnitude(db) 200hpf.res magnitude(db) 20 39.91 79.62 158.9 317 632.5 1.262k 2.518k 5.024k 10.02k 20k -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 figure 14 low-pass / high-pass filter responses
WM8948 production data w pd, may 2011, rev 4.1 36 3d surround the 3d-stereo surround effect is part of the se1 block. this function uses time delays and controlled cross-talk mechanisms to adjust the depth or width of the stereo audio. the 3d-stereo surround effect includes programmable high-pass or low-pass filtering to limit the 3d effect to specific frequency bands if required. the structure of the 3d surround processing is illustrated in figure 15. figure 15 3d surround processing the 3d surround depth is programmable; the default setting is off. the 3d surround processing can also be configured to create a mono mix of the left and right channels. the 3d enhancement is enabled on the left and right channels using the se1_3d_l_ena and se1_3d_r_ena register bits defined in table 13. these bits can be enabled independently of each other. for the derivation of the other associated registers, refer to the configuration tools supplied with the WM8948 evaluation kit. 5-notch filter the 5-notch filter is part of the se1 block. this function allows up to 5 programmable frequency bands to be attenuated. the frequency and width of each notch is configurable; the depth of the attenuation may also be adjusted. the default setting is bypass (off). the notch filters may be enabled on the left and right channels using the se1_notch_l_ena and se1_notch_r_ena register bits defined in table 13. for the derivation of the other associated registers, refer to the configuration tools supplied with the WM8948 evaluation kit. note that, although the 5-notch filter can be enabled on the left/right channels independently, the parameters that define the notch filters apply equally to the left and right channels, when enabled. typical applications for the notch filters are filtering of fixed-frequency noise or resonances; these might arise from a motor (eg. dsc zoom lens motor) or from characteristics of the application housing. example plots of the notch filter response are shown in figure 16.
production data WM8948 w pd, may 2011, rev 4.1 37 notch response - slave mode - fc=1khz, fb=1khz depth 0 to 100% -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 520 1.5k 550 600 650 700 750 800 850 900 1k 1.2k hz notch response - slave mode - fc=1khz, fb=100, 500, 1k, 5k, 10khz - depth=100% -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 20 20k 50 100 200 500 1k 2k 5k 10k hz t t 1khz notch, bandwidth 1khz, depth 0% to 100% in 20% steps 1khz notch, 100% depth, bandwidth 100hz, 500hz, 1khz, 5khz, 10khz notch response - slave mode - fc=200, 500, 1k, 2k, 5k, 10khz, fb=fc/2, depth 100% -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 100 20k 200 500 1k 2k 5k 10k hz t t t t t t t t t t t t t 5 notches, bandwidth fcentre/2, depth 100% figure 16 notch filter responses df1 filter the df1 filter is part of the se1 block. this provides a direct-form 1 standard filter, as illustrated in figure 17. all of the filter coefficients are programmable for the left and right channels independently. the default coefficients give a transparent filter response. figure 17 direct-form 1 standard filter structure
WM8948 production data w pd, may 2011, rev 4.1 38 the df1 response is defined by the following equations: 1 3 1 2 1 3 2 1 1 ] 1 [ ] 1 [ ] [ ] [ ? ? ? + = = ? + ? + = z c z c c x y h n y c n x c n x c n y the df1 filters may be enabled on the left and right channels using the se1_df1_l_ena and se1_df1_r_ena register bits defined in table 13. for the derivation of the other associated registers, refer to the configuration tools supplied with the WM8948 evaluation kit. the df1 filter can be used to implement very complex response patterns, with specific phase and gain responses at different frequencies. typical applications of this type of filter include the application of refinements or compensations to the 3d enhancement or other user-selected filters. retune tm filter the retune? filter is part of the se2 block. this is a very advanced feature that is intended to perform frequency linearization according to the particular needs of the application microphone, loudspeaker or housing. the retune? algorithms can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. the left and right retune? filters are enabled using the se2_retune_l_ena and se2_retune_r_ena register bits defined in table 14. for the derivation of the other retune? configuration parameters, the wolfson wisce? software must be used to analyse the requirements of the application. (refer to wisce for further information.) if desired, one or more sets of register coefficients might be derived for different operating scenarios, and these may be recalled and written to the codec registers as required in the target application. the retune? configuration procedure involves the generation and analysis of test signals as outlined below. to determine the characteristics of the microphone in an application, a test signal is applied to a loudspeaker that is in the acoustic path to the microphone. the received signal through the application microphone is analysed and compared with the received signal from a reference microphone in order to determine the characteristics of the application microphone. to determine the characteristics of the loudspeaker in an application, a test signal is applied to the target application. a reference microphone is positioned in the normal acoustic path of the loudspeaker, and the received signal is analysed to determine how accurately the loudspeaker has reproduced the test signal. 5-band eq the 5-band eq is part of the se2 block. this function allows 5 frequency bands to be controlled. the upper and lower frequency bands are controlled by low-pass and high-pass filters respectively. the middle three frequency bands are bandpass/notch filters. the cut-off / centre frequency of each filter is programmable, and up to 12db gain or attenuation can be selected in each case. the left and right channel parameters may be programmed individually. the 5-band eq may be enabled on the left channel using the se2_5beq_l_ena register bit defined in table 14. for the derivation of the other associated registers, refer to the wisce software.
production data WM8948 w pd, may 2011, rev 4.1 39 typical applications of the 5-band eq include the selection of user-preferences for different music types, such as ?rock?, ?dance? or ?classical? eq profiles. note that when the right channel 5beq filter is disabled the gains for each of the frequency bands must be set to 0db. dynamic range control (drc) drc signal enhancement block 3 (se3) the dynamic range control (drc) forms the se3 block. the drc provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. the drc is configured using the control fields in registers r29 to r35 - see ?dynamic range control?. signal enhancement register controls the se1 ?enable? bits are described in table 13. note that other control fields must also be determined and written to the WM8948 using wisce? or other tools. the registers described below only allow the sub-blocks of se1 to be enabled or disabled. note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers r65 to r98. register address bit label default description r65 (41h) se1_lhpf_ config 1 se1_lhpf_r_ ena 0 se1 right channel low-pass / high- pass filter enable 0 = disabled 1 = enabled 0 se1_lhpf_l_ ena 0 se1 left channel low-pass / high- pass filter enable 0 = disabled 1 = enabled r68 (44h) se1_3d_ config 1 se1_3d_r_ena 0 se1 right channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled 0 se1_3d_l_ena 0 se1 left channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled r71 (47h) se1_notch_ config 1 se1_notch_r _ena 0 se1 right channel notch filters enable 0 = disabled 1 = enabled 0 se1_notch_l _ena 0 se1 left channel notch filters enable 0 = disabled 1 = enabled r92 (5ch) se1_df1_ config 1 se1_df1_r_ ena 0 se1 right channel df1 filter enable 0 = disabled 1 = enabled 0 se1_df1_l_ ena 0 se1 left channel df1 filter enable 0 = disabled 1 = enabled table 13 signal enhancement block 1 (se1)
WM8948 production data w pd, may 2011, rev 4.1 40 the se2 ?enable? bits are described in table 14. note that control fields must also be determined and written to the WM8948 using wisce? or other tools. the registers described below only allow the sub-blocks of se2 to be enabled or disabled. note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers r99 to r175. register address bit label default description r100 (64h) se2_retune _config 1 se2_retune_ r_ena 0 se2 right channel retune? filter enable 0 = disabled 1 = enabled 0 se2_retune_ l_ena 0 se2 left channel retune? filter enable 0 = disabled 1 = enabled r133 (85h) se2_5beq_c onfig 0 se2_5beq_l_ ena 0 se2 left channel 5-band eq enable 0 = disabled 1 = enabled table 14 signal enhancement block 2 (se2) the register controls for signal enhancement block se3 are defined in the ?dynamic range control (drc)? section.
production data WM8948 w pd, may 2011, rev 4.1 41 dynamic range control (drc) the dynamic range controller (drc) is a circuit which can be enabled in the digital playback or digital record path of the WM8948, depending upon the selected dsp mode. the function of the drc is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. the drc can apply compression and automatic level control to the signal path. it incorporates ?anti-clip? and ?quick release? features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. the drc also incorporates a noise gate function, which provides additional attenuation of very low- level input signals. this means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. the drc is enabled as described in table 15. the audio signal path controlled by the drc depends upon the selected dsp configuration mode - see ?dsp core? for details. to remove any dc offsets from the input signal the adc high pass filter must be enabled. the drc will not function correctly unless this filter is enabled. note that the adc hpf bit in register r26(1ah) bit 0 is not enabled by default but must be used if drc_ena is enabled in register r29(1dh) bit 7. register address bit label default description r29 (1dh) drc control 1 7 drc_ena 0 drc enable 0 = disabled 1 = enabled table 15 drc enable drc compression / expansion / limiting the drc supports two different compression regions, separated by a ?knee? (shown as ?knee1? in figure 18) at a specific input amplitude. in the region above the knee, the compression slope drc_hi_comp applies; in the region below the knee, the compression slope drc_lo_comp applies. the drc also supports a noise gate region, where low-level input signals are heavily attenuated. this function can be enabled or disabled according to the application requirements. the drc response in this region is defined by the expansion slope drc_ng_exp. for additional attenuation of signals in the noise gate region, an additional ?knee? can be defined (shown as ?knee2? in figure 18). when this knee is enabled, this introduces an infinitely steep drop- off in the drc response pattern between the drc_lo_comp and drc_ng_exp regions. the overall drc compression characteristic in ?steady state? (i.e. where the input amplitude is near- constant) is illustrated in figure 18. figure 18 drc response characteristic
WM8948 production data w pd, may 2011, rev 4.1 42 the slope of the drc response is determined by register fields drc_hi_comp and drc_lo_comp. a slope of 1 indicates constant gain in this region. a slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). a slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. when the noise gate is enabled, the drc response in this region is determined by the drc_ng_exp register. a slope of 1 indicates constant gain in this region. a slope greater than 1 represents expansion (ie. a change in input amplitude produces a larger change in output amplitude). when the drc_knee2_op knee is enabled (?knee2? in figure 18), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. the drc parameters are listed in table 16. ref parameter description 1 drc_knee_ip input level at knee1 (db) 2 drc_knee_op output level at knee1 (db) 3 drc_hi_comp compression ratio above knee1 4 drc_lo_comp compression ratio below knee1 5 drc_knee2_ip input level at knee2 (db) 6 drc_ng_exp expansion ratio below knee2 7 drc_knee2_op output level at knee2 (db) table 16 drc response parameters the noise gate is enabled when the drc_ng_ena register is set. when the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the drc_lo_comp slope applies to all input signal levels below knee1. the drc_knee2_op knee is enabled when the drc_knee2_op_ena register is set. when this bit is not set, then parameter 7 above is ignored, and the knee2 position always coincides with the low end of the drc_lo_comp region. the ?knee1? point in figure 18 is determined by register fields drc_knee_ip and drc_knee_op. parameter y0, the output level for a 0db input, is not specified directly, but can be calculated from the other parameters, using the equation: the drc compression / expansion / limiting parameters are defined in table 17. register address bit label default description r29 (1dh) drc control 1 8 drc_ng_ena 0 drc noise gate enable 0 = disabled 1 = enabled r32 (20h) drc control 4 12:8 drc_knee2_ip 000000 input signal level at the noise gate threshold ?knee2?. 00000 = -36db 00001 = -37.5db 00010 = -39db ? (-1.5db steps) 11110 = -81db 11111 = -82.5db only applicable when drc_ng_ena = 1. 7:2 drc_knee_ip 000000 input signal level at the compressor ?knee1?. 000000 = 0db
production data WM8948 w pd, may 2011, rev 4.1 43 register address bit label default description 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 = reserved 11111x = reserved r33 (21h) drc control 5 13 drc_knee2_op _ena 0 drc_knee2_op enable 0 = disabled 1 = enabled 12:8 drc_knee2_op 00000 output signal at the noise gate threshold ?knee2?. 00000 = -30db 00001 = -31.5db 00010 = -33db ? (-1.5db steps) 11110 = -75db 11111 = -76.5db only applicable when drc_knee2_op_ena = 1. 7:3 drc_knee_op 00000 output signal at the compressor ?knee1?. 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved 2:0 drc_hi_comp 011 compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = reserved 111 = reserved r35 (23h) drc control 7 9:8 drc_ng_exp 00 noise gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 7:5 drc_lo_comp 000 compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved table 17 drc control registers
WM8948 production data w pd, may 2011, rev 4.1 44 gain limits the minimum and maximum gain applied by the drc is set by register fields drc_mingain, drc_maxgain and drc_ng_mingain. these limits can be used to alter the drc response from that illustrated in figure 18. if the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. the minimum gain in the compression regions of the drc response is set by drc_mingain. the minimum gain in the noise gate region is set by drc_ng_mingain. the minimum gain limit prevents excessive attenuation of the signal path. the maximum gain limit set by drc_maxgain prevents quiet signals (or silence) from being excessively amplified. register address bit label default description r30 (1eh) drc control 2 12:9 drc_ng_ mingain [3:0] 0110 minimum gain the drc can use to attenuate audio signals when the noise gate is active. 0000 = -36db 0001 = -30db 0010 = -24db 0011 = -18db 0100 = -12db 0101 = -6db 0110 = 0db 0111 = 6db 1000 = 12db 1001 = 18db 1010 = 24db 1011 = 30db 1100 = 36db 1101 to 1111 = reserved 4:2 drc_mingain [2:0] 001 minimum gain the drc can use to attenuate audio signals 000 = 0db 001 = -12db (default) 010 = -18db 011 = -24db 100 = -36db 101 = reserved 11x = reserved 1:0 drc_maxgain [1:0] 01 maximum gain the drc can use to boost audio signals (db) 00 = 12db 01 = 18db 10 = 24db 11 = 36db table 18 drc gain limits
production data WM8948 w pd, may 2011, rev 4.1 45 gain readback the gain applied by the drc can be read from the drc_gain register. this is a 16-bit, fixed-point value, which expresses the drc gain as a voltage multiplier. drc_gain is coded as a fixed-point quantity, with an msb weighting of 64. the first 7 bits represent the integer portion; the remaining bits represent the fractional portion. if desired, the value of this field may be interpreted by treating drc_gain as an integer value, and dividing the result by 512, as illustrated in the following examples: drc_gain = 05d4 (hex) = 1380 (decimal) divide by 512 gives 2.914 voltage gain, or 4.645db drc_gain = 0100 (hex) = 256 (decimal) divide by 512 gives 0.5 voltage gain, or -3.01db the drc_gain register is defined in table 19. register address bit label default description r36 (24h) drc status 15:0 drc_gain [15:0] drc gain value. this is the drc gain, expressed as a voltage multiplier. fixed point coding, msb = 64. the first 7 bits are the integer portion; the remaining bits are the fractional part. table 19 drc gain readback dynamic characteristics the dynamic behaviour determines how quickly the drc responds to changing signal levels. note that the drc responds to the peak signal amplitude over a period of time. the drc_atk determines how quickly the drc gain decreases when the signal amplitude is high. the drc_dcy determines how quickly the drc gain increases when the signal amplitude is low. these register fields are described in table 20. note that the register defaults are suitable for general purpose microphone use. register address bit label default description r31 (1fh) drc control 3 7:4 drc_atk [3:0] 0100 attack rate relative to input signal (seconds/6db) 0000 = reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = reserved 3:0 drc_dcy [3:0] 0010 decay rate relative to input signal
WM8948 production data w pd, may 2011, rev 4.1 46 register address bit label default description (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved table 20 drc time constants under the following conditions, it is possible to predict the attack times with an input sine wave: ? decay rate is set at least 8 times the attack rate. ? attack time * input frequency > 1 to estimate the attack time for 10%-90%: ? attack time = register value * 2.24 for example, if drc_atk = 1.45ms/6db, then the attack time for 10%-90% = 1.45ms * 2.24 = 3.25ms. the decay time for 10%-90% can be estimated using the graph in figure 19. figure 19 decay time for 10%-90% vs register value decay rate the decay rate register value read from the horizontal axis and the decay time for 10%-90% read from the vertical axis.
production data WM8948 w pd, may 2011, rev 4.1 47 for example, if drc drc_dcy = 743ms/6db, then the estimate decay time for 10%-90% taken from the graph is 1.0s. anti-clip control the drc includes an anti-clip feature to avoid signal clipping when the input amplitude rises very quickly. this feature uses a feed-forward technique for early detection of a rising signal level. signal clipping is avoided by dynamically increasing the gain attack rate when required. the anti-clip feature is enabled using the drc_anticlip bit. note that the feed-forward processing increases the latency in the input signal path. the drc anti- clip control is described in table 21. register address bit label default description r29 (1dh) drc control 1 1 drc_anticlip 1 drc anti-clip enable 0 = disabled 1 = enabled table 21 drc anti-clip control note that the anti-clip feature operates entirely in the digital domain. it cannot be used to prevent signal clipping in the analogue domain nor in the source signal. analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. the anti-clip and quick release features should not be used at the same time. quick-release control the drc includes a quick-release feature to handle short transient peaks that are not related to the intended source signal. for example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. the quick release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of drc_dcy. the quick-release feature is enabled by setting the drc_qr bit. when this bit is enabled, the drc measures the crest factor (peak to rms ratio) of the input signal. a high crest factor is indicative of a transient peak that may not be related to the intended source signal. if the crest factor exceeds the level set by drc_qr_thr, then the normal decay rate (drc_dcy) is ignored and a faster decay rate (drc_qr_dcy) is used instead. the drc quick-release control bits are described in table 22. register address bit label default description r29 (1dh) drc control 1 2 drc_qr 1 drc quick-release enable 0 = disabled 1 = enabled r34 (22h) drc control 6 3:2 drc_qr_thr [1:0] 00 drc quick-release threshold (crest factor in db) 00 = 12db 01 = 18db 10 = 24db 11 = 30db 1:0 drc_qr_dcy [1:0] 00 drc quick-release decay rate (seconds/6db) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved table 22 drc quick-release control the anti-clip and quick release features should not be used at the same time.
WM8948 production data w pd, may 2011, rev 4.1 48 drc initial value the drc can be set up to a defined initial condition based on the expected signal level when the drc is enabled. this can be set using the drc_init bits in register r35 (23h) bits 4 to 0. note: this does not set the initial gain of the drc. it sets the expected signal level of the drc input signal when the drc is enabled. register address bit label default description r35 (23h) drc control 7 4:0 drc_init 00000 initial value at drc startup 00000 = 0db 00001 = -3.75db ? (-3.75db steps) 11111 = -116.25db digital-to-analogue converter (dac) the WM8948 dacs receive digital input data from the digital audio interface. (note that, depending on the dsp configuration mode, the digital input may first be processed and filtered in the dsp core.) the digital audio data is converted to oversampled bit-streams in the on-chip, true 24-bit digital interpolation filters. the bit-stream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the analogue outputs from the dacs can then be mixed with other analogue inputs before being sent to the analogue output pins (see ?output signal path?). the dacs are enabled by the dacl_ena and dacr_ena register bits. register address bit label default description r3 (03h) power management 2 1 dacr_ena 0 right dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing right channel data from the dac or digital beep generator. 0 dacl_ena 0 left dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing left channel data from the dac or digital beep generator. table 23 dac enable control note: if the WM8948 is to be used in mono mode for playback then the left and right dacs must both be enabled. dac digital volume control the output of the dacs can be digitally amplified or attenuated over a range from -71.625db to +23.625db in 0.375db steps. the volume of each channel can be controlled separately using dacl_vol or dacr_vol. the dac volume is part of the dac digital filters block. the gain for a given eight-bit code x is given by: 0.375 (x-192) db for 1 x 255; mute for x = 0 the dac_vu bit controls the loading of digital volume control data. when dac_vu is set to 0, the dacl_vol or dacr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to dac_vu. this makes it possible to update the gain of both channels simultaneously. the output of the dacs can be digitally muted using the dacl_mute or dacr_mute bits. both dacs are muted simultaneously when the dac_muteall bit is set.
production data WM8948 w pd, may 2011, rev 4.1 49 a digital soft-mute feature is provided in order to avoid sudden glitches in the analogue signal. when dac_vol_ramp is enabled, then all mute, un-mute or volume change commands are implemented as a gradual volume change in the digital domain. the rate at which the volume ramps up is half of the sample freq (fs/2). the dac_vol_ramp register field is described in table 24. register address bit label default description r21 (15h) dac control 1 8 dac_muteall 1 dac digital mute for all channels: 0 = disable mute 1 = enable mute on all channels r22 (16h) dac control 2 4 dac_vol_ramp 1 dac volume ramp control 0 = disabled 1 = enabled r23 (17h) left dac digital vol 12 dac_vu 0 dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 8 dacl_mute 0 left dac digital mute 0 = disable mute 1 = enable mute 7:0 dacl_vol [7:0] 1100_0000 (0db) left dac digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db (see table 25 for volume range) r24 (18h) right dac digital vol 12 dac_vu 0 dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 8 dacr_mute 0 right dac digital mute 0 = disable mute 1 = enable mute 7:0 dacr_vol [7:0] 1100_0000 (0db) right dac volume control 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db (see table 25 for volume range) table 24 dac digital volume control
WM8948 production data w pd, may 2011, rev 4.1 50 dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 18.000 31h -53.625 71h -29.625 b1h -5.625 f1h 18.375 32h -53.250 72h -29.250 b2h -5.250 f2h 18.750 33h -52.875 73h -28.875 b3h -4.875 f3h 19.125 34h -52.500 74h -28.500 b4h -4.500 f4h 19.500 35h -52.125 75h -28.125 b5h -4.125 f5h 19.875 36h -51.750 76h -27.750 b6h -3.750 f6h 20.250 37h -51.375 77h -27.375 b7h -3.375 f7h 20.625 38h -51.000 78h -27.000 b8h -3.000 f8h 21.000 39h -50.625 79h -26.625 b9h -2.625 f9h 21.375 3ah -50.250 7ah -26.250 bah -2.250 fah 21.750 3bh -49.875 7bh -25.875 bbh -1.875 fbh 22.125 3ch -49.500 7ch -25.500 bch -1.500 fch 22.500 3dh -49.125 7dh -25.125 bdh -1.125 fdh 22.875 3eh -48.750 7eh -24.750 beh -0.750 feh 23.250 3fh -48.375 7fh -24.375 bfh -0.375 ffh 23.625 table 25 dac digital volume range
production data WM8948 w pd, may 2011, rev 4.1 51 dac auto-mute the dac digital mute and volume controls are described earlier in table 24. the dac also incorporates an analogue auto-mute, which is enabled by setting dac_automute. when the auto-mute is enabled, and a series of 1024 consecutive zero-samples is detected, the dac output is muted in order to attenuate noise that might be present in output signal path. the dac resumes normal operation as soon as digital audio data is detected. register address bit label default description r21 (15h) dac control 1 4 dac_automute 1 dac auto-mute control 0 = disabled 1 = enabled table 26 dac auto mute note: the dac_automute bit should not be set when the beep generator is used. dac sloping stopband filter two dac filter types are available, selected by the register bit dac_sb_flt. when operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (dac_sb_flt=1) to reduce out-of-band noise which can be audible at low dac sample rates. see ?digital filter characteristics? for details of dac filter characteristics. register address bit label default description r22 (16h) dac control 2 0 dac_sb_flt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode table 27 dac sloping stopband filter
WM8948 production data w pd, may 2011, rev 4.1 52 digital beep generator the WM8948 provides a digital signal generator which can be used to inject an audio tone (beep) into the dac signal path. the output of the beep generator is digitally mixed with the dac outputs, after the dac digital volume. the beep is enabled using beep_ena. the beep function creates an approximation of a sine wave. the audio frequency is set using beep_rate. the beep volume is set using beep_gain. note that the volume of the digital beep generator is not affected by the dac volume or dac mute controls. the dac_automute bit should not be set when the beep generator is used. the digital beep generator control fields are described in table 28. register address bit label default description r37 (25h) beep control 1 6:3 beep_gain [3:0] 0000 digital beep volume control 0000 = mute 0001 = -83db 0010 = -77db ? (6db steps) 1111 = +1db 2:1 beep_rate [1:0] 01 b eep waveform control 00 = reserved 01 = 1khz 10 = 2khz 11 = 4khz 0 beep_ena 0 digital b eep enable 0 = disabled 1 = enabled note that the dac and associated signal path needs to be enabled when using the digital beep. table 28 digital beep generator note: the beep generator is clocked by the left channel dac clock. if the beep signal is used on the right channel only, the left channel dac must be enabled.
production data WM8948 w pd, may 2011, rev 4.1 53 output signal path the WM8948 provides two line output mixers and two speaker output mixers. multiple inputs to each mixer provide a high degree of flexibility to route different signal paths to each of the four analogue outputs. the dac outputs can be routed to the mixers either directly or in inverted phase. this makes it easy to generate differential (btl) or mono output signals. the auxiliary inputs aux1/2 may be routed directly to the speaker outputs, bypassing the speaker pgas and mixers. this can be used to provide a fixed-gain signal path for a ?pc beep? or similar application. the output signal paths and associated control registers are illustrated in figure 20. note that the speaker outputs are intended to drive a mono headset or speaker (in btl configuration). they are not designed to drive stereo speakers directly. figure 20 output signal paths
WM8948 production data w pd, may 2011, rev 4.1 54 output signal paths enable each analogue output pin can be independently enabled or disabled using the register bits described in table 29. the speaker output pgas and mixers can also be controlled. register address bit label default description r3 (03h) power management 2 15 outr_ena 0 lineoutr enable 0 = disabled 1 = enabled 14 outl_ena 0 lineoutl enable 0 = disabled 1 = enabled 13 spkr_pga_ena 0 s peaker right pga enable 0 = disabled 1 = enabled 12 spkl_pga_ena 0 speaker left pga enable 0 = disabled 1 = enabled 11 spkr_spkvdd_ ena 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_op_ena. when powering down spkoutr, the spkr_spkvdd_ena bit should be reset first. 10 spkl_spkvdd_ ena 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_op_ena. when powering down spkoutl, the spkl_spkvdd_ena bit should be reset first 7 spkr_op_ena 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_spkvdd_ena. w hen powering up spkoutr, the spkr_op_ena bit s hould be enabled first. 6 spkl_op_ena 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_spkvdd_ena. when powering up spkoutl, the spkl_op_ena bit should be enabled first 3 spkr_mix_ena 0 right s peaker output mixer enable 0 = disabled 1 = enabled 2 spkl_mix_ena 0 left speaker output mixer enable 0 = disabled 1 = enabled table 29 output signal paths enable
production data WM8948 w pd, may 2011, rev 4.1 55 to enable the output pgas and mixers, the reference voltage vmid and the bias current must also be enabled. see ?reference voltages and master bias? for details of the associated controls vmid_sel and bias_ena. note that the line outputs, speaker outputs and speaker pga mixers are all muted by default. the required signal paths must be un-muted using the control bits described in the respective tables below. line output mixer control the line output mixer controls are described in table 30 for the left channel (mixoutl) and table 31 for the right channel (mixoutr). these allow any of the dacl/r, inverted dacl/r, aux1/2 and one of the adc bypass signals to be mixed. the output of each mixer can be muted also, using the linel_mute and liner_mute bits. care should be taken when mixing more than one path to the line output mixers in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path to facilitate this. note that the attenuation control fields dacl_to_outl_atten and dacr_to_outl_atten control both the dac and the inverted dac mixer paths to the left channel output mixer. the equivalent applies to dacl_to_outr_atten and dacr_to_outr_atten also. note that the dac input levels may also be controlled by the dac digital volume control - see ?digital to analogue converter (dac)? for further details. when the aux1 or aux2 pin is used as an audio input, that pin must be configured for audio using the aux1_audio or aux2_audio register bits. these bits are defined in table 2 (see ?analogue input signal path?). register address bit label default description r42 (2ah) output ctrl 8 linel_mute 1 lineoutl output mute 0 = disable mute 1 = enable mute r49 (31h) line l mixer control 1 6 bypl_to_outl 0 left input pga (adc bypass) to left output mixer select 0 = disabled 1 = enabled 5 mdacl_to_ outl 0 inverted left dac to left output mixer select 0 = disabled 1 = enabled 4 mdacr_to_ outl 0 inverted right dac to left output mixer select 0 = disabled 1 = enabled 3 dacl_to_outl 0 left dac to left output mixer select 0 = disabled 1 = enabled 2 dacr_to_outl 0 right dac to left output mixer select 0 = disabled 1 = enabled 1 aux2_to_outl 0 aux2 audio input to left output mixer select 0 = disabled 1 = enabled
WM8948 production data w pd, may 2011, rev 4.1 56 register address bit label default description 0 aux1_to_outl 0 aux1 audio input to left output mixer select 0 = disabled 1 = enabled r51 (33h) line l mixer control 2 6 bypl_to_outl _atten 0 left input pga (adc bypass) to left output mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_outl _atten 0 left dac to left output mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_outl _atten 0 right dac to left output mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_outl _atten 0 aux2 audio input to left output mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_outl _atten 0 aux1 audio input to left output mixer attenuation 0 = 0db 1 = -6db attenuation table 30 left output mixer (mixoutl) control register address bit label default description r42 (2ah) output ctrl 9 liner_mute 1 lineoutr output mute 0 = disable mute 1 = enable mute r50 (32h) line r mixer control 1 6 bypr_to_outr 0 right i nput pga (adc bypass) to right output mixer select 0 = disabled 1 = enabled 5 mdacl_to_ outr 0 inverted left dac to right output mixer select 0 = disabled 1 = enabled 4 mdacr_to_ outr 0 inverted right dac to right output mixer select 0 = disabled 1 = enabled 3 dacl_to_outr 0 left dac to right output mixer select 0 = disabled 1 = enabled 2 dacr_to_outr 0 right dac to right output mixer select 0 = disabled 1 = enabled 1 aux2_to_outr 0 aux2 audio input to right output mixer select 0 = disabled 1 = enabled
production data WM8948 w pd, may 2011, rev 4.1 57 register address bit label default description 0 aux1_to_outr 0 aux1 audio input to right output mixer select 0 = disabled 1 = enabled r52 (34h) line r mixer control 2 6 bypr_to_outr _atten 0 right input pga (adc bypass) to right output mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_outr _atten 0 left dac to right output mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_outr _atten 0 right dac to right output mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_outr _atten 0 aux2 audio input to right output mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_outr _atten 0 aux1 audio input to right output mixer attenuation 0 = 0db 1 = -6db attenuation table 31 right output mixer (mixoutr) control speaker pga mixer control the speaker pga mixer controls are described in table 32 for the left channel (mixspkl) and table 33 for the right channel (mix spkr). these allow any of the dacl/r, inverted dacl/r, aux1/2 and one of the adc bypass signals to be mixed. the output of each pga mixer can be muted also, using the spkl_mix_mute and spkr_mix_mute bits. note that the output from the speaker pga mixer is also controlled by the speaker pga volume control and the speaker output control described in the following sections. care should be taken when enabling more than one path to the speaker pga mixers in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path to facilitate this. note that the attenuation control fields dacl_to_pgal_atten and dacr_to_pgal_atten control both the dac and the inverted dac mixer paths to the left speaker pga mixer. the equivalent applies to dacl_to_pgar_atten and dacr_to_pgar_atten also. note that the dac input levels may also be controlled by the dac digital volume control - see ?digital to analogue converter (dac)? for further details. when the aux1 or aux2 pin is used as an audio input, that pin must be configured for audio using the aux1_audio or aux2_audio register bits. these bits are defined in table 2 (see ?analogue input signal path?).
WM8948 production data w pd, may 2011, rev 4.1 58 register address bit label default description r3 (03h) power management 1 4 spkl_mix_ mute 1 left speaker pga mixer mute 0 = disable mute 1 = enable mute r43 (2bh) spk mixer control 1 6 bypl_to_pgal 0 left input pga (adc bypass) to left speaker pga mixer select 0 = disabled 1 = enabled 5 mdacl_to_ pgal 0 inverted left dac to left speaker pga mixer select 0 = disabled 1 = enabled 4 mdacr_to_ pgal 0 inverted right dac to left speaker pga mixer select 0 = disabled 1 = enabled 3 dacl_to_pgal 0 left dac to left speaker pga mixer select 0 = disabled 1 = enabled 2 dacr_to_pgal 0 right dac to left speaker pga mixer select 0 = disabled 1 = enabled 1 aux2_to_pgal 0 aux2 audio input to left speaker pga mixer select 0 = disabled 1 = enabled 0 aux1_to_pgal 0 aux1 audio input to left speaker pga mixer select 0 = disabled 1 = enabled r45 (2dh) spk mixer control 3 6 bypl_to_pgal _atten 0 left input pga (adc bypass) to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_pgal _atten 0 left dac to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_pgal _atten 0 right dac to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_pgal _atten 0 aux2 audio input to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_pgal _atten 0 aux1 audio input to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation table 32 left speaker pga mixer (mixspkl) control
production data WM8948 w pd, may 2011, rev 4.1 59 register address bit label default description r3 (03h) power management 1 5 spkr_mix_ mute 1 right speaker pga mixer mute 0 = disable mute 1 = enable mute r44 (2ch) spk mixer control 2 6 bypr_to_pgar 0 right i nput pga (adc bypass) to right speaker pga mixer select 0 = disabled 1 = enabled 5 mdacl_to_ pgar 0 inverted left dac to right speaker pga mixer select 0 = disabled 1 = enabled 4 mdacr_to_ pgar 0 inverted right dac to right speaker pga mixer select 0 = disabled 1 = enabled 3 dacl_to_pgar 0 left dac to right speaker pga mixer select 0 = disabled 1 = enabled 2 dacr_to_pgar 0 right dac to right speaker pga mixer select 0 = disabled 1 = enabled 1 aux2_to_pgar 0 aux2 audio input to right speaker pga mixer select 0 = disabled 1 = enabled 0 aux1_to_pgar 0 aux1 audio input to right speaker pga mixer select 0 = disabled 1 = enabled r46 (2eh) spk mixer control 4 6 bypr_to_pgar _atten 0 right input pga (adc bypass) to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_pgar _atten 0 left dac to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_pgar _atten 0 right dac to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_pgar _atten 0 aux2 audio input to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_pgar _atten 0 aux1 audio input to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation table 33 right speaker pga mixer (mi xspkr) control
WM8948 production data w pd, may 2011, rev 4.1 60 speaker pga volume control the volume control of the left and right speaker pgas can be independently adjusted using the spkl_vol and spkr_vol register fields as described in table 34. the gain range is -57db to +6db in 1db steps. note that the output from the speaker pga volume control is an input to the speaker output control described in the following section. to prevent "zipper noise", a zero-cross function is provided on the speaker pgas. when this feature is enabled, volume updates will not take place until a zero-crossing is detected. in the case of a long period without zero-crossings, a timeout function is provided. when the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. the timeout clock is enabled using toclk_ena. see ?clocking and sample rates? for the definition of this bit. the spk_vu bits control the l oading of the speaker pga volume data. when spk_vu is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. the left and right speaker pga volume settings are both updated when a 1 is written to either spk_vu bit. this makes it possible to update the gain of the left and right output paths simultaneously. the speaker pga volume control register fields are described in table 34. register address bit label default description r47 (2fh) left spk volume ctrl 8 spk_vu 0 s peaker pga volume update writing a 1 to this bit will cause the left and right speaker pga volumes to be updated simultaneously. 7 spkl_zc 0 left speaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 spkl_pga_ mute 1 left speaker pga mute 0 = disable mute 1 = enable mute 5:0 spkl_vol 11_1001 (0db) left speaker pga volume 00_0000 = -57db gain 00_0001 = -56db ? 11_1001 = 0db ... 11_1111 = +6db (see table 35 for volume range) r48 (30h) right spk volume ctrl 8 spk_vu 0 s peaker pga volume update writing a 1 to this bit will cause the left and right speaker pga volumes to be updated simultaneously. 7 spkr_zc 0 right s peaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 spkr_pga_ mute 1 right speaker pga mute 0 = disable mute 1 = enable mute
production data WM8948 w pd, may 2011, rev 4.1 61 register address bit label default description 5:0 spkr_vol 11_1001 (0db) right speaker pga volume 00_0000 = -57db gain 00_0001 = -56db ? 11_1001 = 0db ... 11_1111 = +6db (see table 35 for volume range) table 34 speaker pga volume control pga gain setting volume (db) pga gain setting volume (db) 00h -57 20h -25 01h -56 21h -24 02h -55 22h -23 03h -54 23h -22 04h -53 24h -21 05h -52 25h -20 06h -51 26h -19 07h -50 27h -18 08h -49 28h -17 09h -48 29h -16 0ah -47 2ah -15 0bh -46 2bh -14 0ch -45 2ch -13 0dh -44 2dh -12 0eh -43 2eh -11 0fh -42 2fh -10 10h -41 30h -9 11h -40 31h -8 12h -39 32h -7 13h -38 33h -6 14h -37 34h -5 15h -36 35h -4 16h -35 36h -3 17h -34 37h -2 18h -33 38h -1 19h -32 39h 0 1ah -31 3ah +1 1bh -30 3bh +2 1ch -29 3ch +3 1dh -28 3dh +4 1eh -27 3eh +5 1fh -26 3fh +6 table 35 speaker pga volume range
WM8948 production data w pd, may 2011, rev 4.1 62 speaker output control each speaker output has its own output mixer. this allows the output of the respective speaker pga to be enabled or disabled, and also allows the auxiliary input aux1 to be routed directly to either speaker output. the two speaker outputs can be muted also, using the spkr_op_mute and spkl_op_mute. the aux1 path can be used to provide a fixed-gain signal path that is unaffected by the speaker pga setting. this feature is intended for a ?pc beep? or similar applications. care should be taken when enabling more than one path to the speaker output mixers in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path to facilitate this. when the aux1 pin is used as an audio input, that pin must be configured for audio using the aux1_audio register bit. this bit is defined in table 2 (see ?analogue input signal path?). the speaker output control registers are described in table 36. register address bit label default description r3 (03h) power management 1 9 spkr_op_mute 1 spkoutr output mute 0 = disable mute 1 = enable mute 8 spkl_op_mute 1 spkoutl output mute 0 = disable mute 1 = enable mute r43 (2bh) spk mixer control 1 8 aux1_to_spkl 0 aux1 audio i nput to left speaker output select 0 = disabled 1 = enabled 7 pgal_to_spkl 0 left s peaker pga mixer to left speaker output select 0 = disabled 1 = enabled r44 (2ch) spk mixer control 2 8 aux1_to_spkr 0 aux1 audio i nput to right speaker output select 0 = disabled 1 = enabled 7 pgar_to_spkr 0 right speaker pga mixer to right speaker output select 0 = disabled 1 = enabled r45 (2dh) spk mixer control 3 8 aux1_to_spkl _atten 0 aux1 audio input to left speaker output attenuation 0 = 0db 1 = -6db attenuation 7 pgal_to_spkl _atten 0 left speaker pga mixer to left speaker output attenuation 0 = 0db 1 = -6db attenuation r46 (2eh) spk mixer control 4 8 aux1_to_spkr _atten 0 aux1 audio input to right speaker output attenuation 0 = 0db 1 = -6db attenuation 7 pgar_to_spkr _atten 0 right speaker pga mixer to right speaker output attenuation 0 = 0db 1 = -6db attenuation table 36 speaker output control
production data WM8948 w pd, may 2011, rev 4.1 63 analogue outputs the line outputs and speaker outputs are highly configurable and may be used in many different ways. the output mixers can be configured to generate mono or stereo, single-ended or differential outputs. the class ab speaker output driver can deliver up to 400mw into an 8 speaker in btl mode. alternatively, the speaker outputs can deliver 40mw to a stereo 16 headphone load. line outputs the line outputs lineoutl and lineoutr are the external connections to the line output mixers. in a typical application, these will deliver a stereo pair of outputs in single-ended configuration. for stereo line output, the left and right output mixers are used to generate the left and right output signals respectively. a differential mono (left+right) dac output may be generated at the line outputs by routing an inverted dac signal to one output and the non-inverted signal from the other dac to the other line output. a differential output from a single dac may be generated at the line outputs by routing the inverted dac signal to one output and the non-inverted dac signal to the other. when the speaker outputs are similarly configured for the other dac channel, then stereo differential output is possible. speaker outputs the speaker outputs spkoutl and spkoutr are the external c onnections to the speaker output mixers. these outputs are intended for a mono speaker or headphone in btl configuration or for a stereo line load. for stereo line configuration, the left and right speaker output mixers are used to generate the left and right output signals respectively. for mono speaker or headphone configuration, a btl output from the dacs may be generated by routing an inverted dac signal to one speaker output and the non-inverted signal from the other dac to the other speaker output. the auxiliary inputs aux1 or aux2 may be routed to the mono speaker by enabling the respective signal path in either the left or right speaker output mixer. (note that these signals should not be enabled in both mixers at once; this will lead to cancellation at the btl output.) note that a differential output from a single dac may be generated at the speaker outputs by routing the inverted dac signal to one output and the non-inverted dac signal to the other. when the line outputs are similarly configured for the other dac channel, then stereo differential output is possible. external components for line output in single-ended output configurations, dc blocking capacitors are required at the output pins (lineoutl, lineoutr, spkoutl and spkoutr). see ?applications information? for details of these components. note that these components are not required for differential (btl) output modes. ldo regulator the WM8948 provides an internal ldo which provides a regulated voltage for use as in internal supply and reference, which can also be used to power external circuits. the ldo is enabled by setting the ldo_ena register bit. the ldo supply is drawn from the ldovdd pin; the ldo output is provided on the ldovout pin. the ldo requires a reference voltage and a bias source; these are configured as described below. the ldo bias source is selected using ldo_bias_src. care is required during start-up to ensure that the selected bias is enabled; the master bias will not normally be available at initial start-up, and the fast bias should be selected in the first instance.
WM8948 production data w pd, may 2011, rev 4.1 64 the ldo reference voltage can be selected using ldo_ref_sel; this allows selection of either the internal bandgap reference or one of the vmid resistor strings. when vmid is selected as the reference, then ldo_ref_sel_fast selects either the normal vmid reference or the fast-start vmid reference. care is required during start-up to ensure that the selected reference is enabled; the vmid references are enabled using vmid_ena and vmid_fast_start as described in table 40 and table 41 respectively. the internal bandgap reference is nominally 1.5v. note that this value is not trimmed and may vary significantly (+/-10%) between different devices. when using this reference, the internal bandgap reference must be enabled by setting the bg_ena register, as described in table 37. the bandgap voltage can be adjusted using the bg_ vsel register as descri bed in table 39. the ldo output voltage is set using the ldo_vsel register, which sets the ratio of the output voltage to the ldo reference voltage. see table 38 for ldo output voltages. example1: how to generate an ldovout voltage of 3.0v from a 3.3v ldovdd supply voltage. ldo_ref_sel = 0 (vmid as the reference voltage) vmid = 1.5v (vmid_ref_sel = 0, vmid_ctrl = 0) ldovout = vref * 1.97 = 1.5v * 1.97 = 2.96v. (see table 38) example2: generating an ldovout voltage of 2.4v from a 3.0v ldovdd supply. for maximum signal swing the vmid voltage should be half of the ldovout voltage. for ldovout of 2.4v the optimum vmid voltage is 1.2v. select the vmid source voltage as ldovout (vmid_ref_sel = 1) and the vmid ratio as 1/2 (vmid_ctrl = 1). this gives vmid = 1.2v. vmid cannot be used as the ldo reference voltage so use the bandgap voltage as the ldo reference voltage (ldo_ref_sel = 1, bg_ena = 1). the default bandgap voltage is 1.467v. for ldovout of 2.4v ldovsel should be set to 2.4v / 1.467v = 1.636. referring to table 38 ldo_vsel = 03h will give ldovout = 1.467 * 1.66 = 2.435v. note that the bandgap voltage is not trimmed so if required the bandgap voltage can be changed (bg_vsel ? see table 39) to get closer to the required voltage. by default, the ldo output is actively discharged to gnd through internal resistors when the ldo is disabled. this is desirable in shut-down to prevent any external connections being affected by the internal circuits. the ldo output can be set to float when the ldo is disabled; this is selected by setting the ldo_op_flt bit. this option should be selected if the ldo is bypassed and an external voltage is applied to ldovout. the ldo output is monitored for voltage accuracy. the ldo undervoltage status can be read at any time from the ldo_uv_sts bit, as described in table 37. this bit can be polled at any time, or may output directly on a gpio pin, or may be used to generate interrupt events. register address bit label default description r17 (11h) status flags 0 ldo_uv_sts 0 ldo undervoltage status 0 = normal 1 = undervoltage r53 (35h) ldo 15 ldo_ena 0 ldo enable 0 = disabled 1 = enabled 14 ldo_ref_sel_ fast 0 ldo voltage reference select 0 = vmid (normal) 1 = vmid (fast start) this field is only effective when ldo_ref_sel = 0
production data WM8948 w pd, may 2011, rev 4.1 65 register address bit label default description 13 ldo_ref_sel 0 ldo voltage reference select 0 = vmid 1 = bandgap 12 ldo_opflt 0 ldo output float 0 = disabled (output discharged when disabled) 1 = enabled (output floats when disabled) 5 ldo_bias_src 0 ldo bias source select 0 = master bias 1 = start-up bias 4:0 ldo_vsel 00111 ldo voltage select (sets the ldo output as a ratio of the selected voltage reference. the voltage reference is set by ldo_ref_sel.) 00111 = vref x 1.97 (default) (see table 38 for range) r54 (36h) bandgap 15 bg_ena 0 bandgap reference control 0 = disabled 1 = enabled 4:0 bg_vsel[4:0] 01010 bandgap voltage select (sets the bandgap voltage) 00000 = 1.200v ? 26.7mv steps 01010 = 1.467v (default) ? 01111 = 1.600v 10000 to 11111 = reserved (see table 39 for values) table 37 ldo regulator control ldo_vsel [4:0] ldo output ldo_vsel [4:0] ldo output 00h vref x 1.42 10h vref x 2.85 01h vref x 1.50 11h vref x 3.00 02h vref x 1.58 12h vref x 3.16 03h vref x 1.66 13h vref x 3.32 04h vref x 1.74 14h vref x 3.49 05h vref x 1.82 15h vref x 3.63 06h vref x 1.90 16h vref x 3.79 07h vref x 1.97 17h vref x 3.95 08h vref x 2.06 18h vref x 4.12 09h vref x 2.13 19h vref x 4.28 0ah vref x 2.21 1ah vref x 4.42 0bh vref x 2.29 1bh vref x 4.58 0ch vref x 2.37 1ch vref x 4.75 0dh vref x 2.45 1dh vref x 4.90 0eh vref x 2.53 1eh vref x 5.06 0fh vref x 2.69 1fh vref x 5.23 note - vref is the applicable voltage reference, selected by ldo_ref_sel. table 38 ldo output voltage control
WM8948 production data w pd, may 2011, rev 4.1 66 bg_vsel [4:0] bg voltage (v) bg_vsel [4:0] bg voltage (v) 00h 1.200 08h 1.414 01h 1.227 09h 1.440 02h 1.253 0ah 1.467 03h 1.280 0bh 1.494 04h 1.307 0ch 1.520 05h 1.334 0dh 1.547 06h 1.360 0eh 1.574 07h 0.387 0fh 1.600 table 39 bandgap voltage control reference voltages and master bias this section describes the analogue reference voltage and bias current controls. it also describes the vmid soft-start circuit for pop suppressed start-up and shut-down. the analogue circuits in the WM8948 require a mid-rail analogue reference voltage, vmid. this reference is generated via a programmable resistor chain. together with the external decoupling capacitor (connected to the vmidc pin), the programmable resistor chain results in a slow, normal or fast charging characteristic on the vmid reference. this is enabled using vmid_ena and vmid_sel. the different resistor options controlled by vmid_sel can be used to optimise the reference for normal operation, low power standby or for fast start-up as described in table 40. the vmid resistor chain can be powered from the ldo output (ldovout) or from the ldo supply (ldovdd). this is selected using vmid_ref_sel. note that when vmid is selected as the ldo reference voltage, vmid cannot be generated from the ldovout supply voltage (vmid_ref_sel = 1) and must be generated from the ldovdd supply voltage (vmid_ref_sel = 0). the vmid ratio can be selected using vmid_ctrl. this selects the ratio of vmid to the supply voltage that has been selected by vmid_ref_sel. vmid should be half of the ldovout supply voltage for maximum voltage swing. in the case where vmid_ref_sel has selected the ldovout supply voltage output, then vmid_ctrl should select the ratio ?1/2?. in the case where vmid_ref_sel has selected the ldovdd supply voltage, then the alternate ratio ?5/11? may be preferred provided ldovddd = 3.3v and ldovout = 3.0v. note that the ?5/11? ratio is designed for the case where ldovdd = 3.3v and ldovout = 3.0v. this results in a vmid = 3.3v x (5/11) = 1.5v which is half of the ldovout voltage. if these conditions are not being used or the ldo has been bypassed then vmid_ref should be set to select ldovout as the vmid source and vmid_ctrl should be set to select the ratio ?1/2?. the analogue circuits in the WM8948 require a bias current. the normal bias current is enabled by setting bias_ena. note that the normal bias current source requires vmid to be enabled also.
production data WM8948 w pd, may 2011, rev 4.1 67 the master reference and bias control bits are defined in table 40. register address bit label default description r7 (07h) additional control 10 vmid_ref_sel 0 vmid source select 0 = ldo supply (ldovdd) 1 = ldo output (ldovout) 9 vmid_ctrl 0 vmid ratio control sets the ratio of vmid to the source selected by vmid_ref_sel 0 = 5/11 1 = 1/2 4 vmid_ena 0 vmid enable 0 = disabled 1 = enabled r2 (02h) power management 1 3 bias_ena 0 master bias enable 0 = disabled 1 = enabled 1:0 vmid_sel [1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start- up) table 40 reference voltages and master bias enable a pop-suppressed start-up requires vmid to be enabled smoothly, without the step change normally associated with the initial stage of the vmid capacitor charging. a pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the vmid reference voltage being applied. the WM8948 incorporates pop-suppression circuits which address these requirements. an alternate bias current source (start-up bias) is provided for pop-free start-up; this is enabled by the startup_bias_ena register bit. the start-up bias is selected (in place of the normal bias) using the bias_src bit. it is recommended that the start-up bias is used during start-up, before switching back to the higher quality, normal bias. a soft-start circuit is provided in order to control the switch-on of the vmid reference. the soft-start control circuit offers two slew rates for enabling the vmid reference; these are selected and enabled by vmid_ramp. when the soft-start circuit is enabled prior to enabling vmid_sel, the reference voltage rises smoothly, without the step change that would otherwise occur. it is recommended that the soft-start circuit and the output signal path be enabled before vmid is enabled by vmid_sel. a soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator. the soft shut-down of vmid is achieved by setting vmid_ramp, startup_bias_ena and bias_src to select the start-up bias current and soft-start circuit prior to setting vmid_sel=00. the internal ldo (described in the previous section) requires a voltage reference. under normal operating conditions, this is provided from vmid, via the register controls described in table 40. note, however, that vmid is normally generated from the ldo output. therefore, an alternative voltage reference is required for start-up, which is not dependent on the ldo output. the vmid_fast_start bit enables a ?fast-start? reference powered from ldovdd. this alternate vmid can be selected as the ldo reference using the ldo_ref_sel_fast bit as described in table 37.
WM8948 production data w pd, may 2011, rev 4.1 68 the vmid soft-start and fast start register controls are defined in table 41. register address bit label default description r7 (07h) additional control 11 vmid_fast_ start 0 vmid (fast-start) enable 0 = disabled 1 = enabled 8 startup_bias_ ena 0 start-up bias enable 0 = disabled 1 = enabled 7 bias_src 0 bias source select 0 = normal bias 1 = start-up bias 6:5 vmid_ramp [1:0] 00 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = normal soft start 11 = slow soft start table 41 soft start control pop suppression control the WM8948 incorporates a number of features which are designed to suppress pops normally associated with start-up, shut-down or signal path control. these include the option to maintain an analogue output to vmid even when the output driver is disabled. in addition, there is the ability to actively discharge an output to gnd. note that, to achieve maximum benefit from these features, careful attention may be required to the sequence and timing of these controls. disabled output control the line outputs and speaker outputs are biased to vmid in normal operation. in order to avoid audible pops caused by a disabled signal path dropping to gnd, the WM8948 can maintain these connections at vmid when the relevant output stage is disabled. this is achieved by connecting a buffered vmid reference to the output. the buffered vmid reference is enabled by setting vmid_buf_ena. this is applied to any disabled outputs, provided that the respective _vmid_op_ena bit is also set. the output resistance can be either 1k or 20k , depending on the respective _vroi register bit. the disabled output control bits are described in table 42. see ?output signal path? for details of how to disable any of the audio outputs.
production data WM8948 w pd, may 2011, rev 4.1 69 register address bit label default description r2 (02h) power management 1 2 vmid_buf_ena 0 vmid buffer enable. (the buffered vmid may be applied to disabled input and output pins.) 0 = disabled 1 = enabled r42 (2ah) output ctrl 13 spkr_vmid_op _ena 0 buffered vmid to spkoutr enable 0 = disabled 1 = enabled 12 spkl_vmid_op _ena 0 buffered vmid to spkoutl e nable 0 = disabled 1 = enabled 11 liner_vmid_op _ena 0 buffered vmid to lineoutr enable 0 = disabled 1 = enabled 10 linel_vmid_op _ena 0 buffered vmid to lineoutl enable 0 = disabled 1 = enabled 1 spk_vroi 0 buffered vref to spkoutl / spkoutr resistance (disabled outputs) 0 = approx 20k 1 = approx 1k 0 line_vroi 0 buffered vref to lineoutl / lineoutr resistance (disabled outputs) 0 = approx 20k 1 = approx 1k table 42 disabled output control output discharge control the line outputs and speaker outputs can be actively discharged to gnd through internal resistors if desired. this is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start vmid reference voltage. this is also desirable in shut-down to prevent the external connections from being affected by the internal circuits. the individual control bits for discharging each audio output are described in table 43.
WM8948 production data w pd, may 2011, rev 4.1 70 register address bit label default description r42 (2ah) output ctrl 7 spkr_disch 0 discharges spkoutr output via approx 4k resistor 0 = not active 1 = actively discharging spkoutr 6 spkl_disch 0 discharges spkoutl output via approx 4k resistor 0 = not active 1 = actively discharging spkoutl 5 liner_disch 0 discharges lineoutr output via approx 4k resistor 0 = not active 1 = actively discharging lineoutr 4 linel_disch 0 discharges lineoutl output via approx 4k resistor 0 = not active 1 = actively discharging lineoutl table 43 output discharge control digital audio interface the digital audio interface is used for inputting dac data into the WM8948 and outputting adc data from it. it uses four pins: ? adcdat: adc data output ? dacdat: dac data input ? lrclk: dac and adc data alignment clock ? bclk: bit clock, for synchronisation master and slave mode operation the digital audio interface can be configured as a master or a slave interface, using the mstr register bit. the two modes are illustrated in figure 21 and figure 22. figure 21 master mode figure 22 slave mode in master mode, lrclk and bclk are configured as outputs, and the WM8948 controls the timing of the data transfer on the adcdat and dacdat pins. in master mode, the lrclk frequency is determined automatically according to the sample rate (see ?clocking and sample rates?). the bclk frequency is set by the bclk_div register. bclk_div must be set to an appropriate value to ensure that there are sufficient bclk cycles to transfer the complete data words from the adcs and to the dacs.
production data WM8948 w pd, may 2011, rev 4.1 71 in slave mode, lrclk and bclk are configured as inputs, and the data timing is controlled by an external master. register address bit label default description r6 (06h) clock gen control 3:1 bclk_div [2:0] 011 bclk frequency (master mode) 000 = sysclk 001 = sysclk / 2 010 = sysclk / 4 011 = sysclk / 8 100 = sysclk / 16 101 = sysclk / 32 110 = reserved 111 = reserved 0 mstr 0 digital audio interface mode select 0 = slave mode 1 = master mode table 44 digital audio interface control audio data formats three basic audio data formats are supported: ? left justified ? i 2 s ? dsp mode all four of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. pcm operation is supported using the dsp mode. the WM8948 can control the channel selection between the adcs and the adcdat pin. similarly, the channel selection between the dacdat pin and the dacs is selectable. digital inversion of the adc or dac data is also possible. the register bits controlling audio data format and channel configuration are described in table 45. register address bit label default description r4 (04h) audio interface 9 adcr_src 1 right digital audio interface source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 8 adcl_src 0 left digital audio interface source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 7 dacr_src 1 right dac data source select 0 = right dac outputs left interface data 1 = right dac outputs right interface data 6 dacl_src 0 left dac data source select 0 = left dac outputs left interface data 1 = left dac outputs right interface data
WM8948 production data w pd, may 2011, rev 4.1 72 register address bit label default description 5 bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted 4 lrclk_inv 0 lrclk polarity / dsp mode a-b select. right, left and i 2 s modes ? lrclk polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrclk rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrclk rising edge (mode b) 3:2 wl [1:0] 10 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits note - see ?companding? for the selection of 8-bit mode. 1:0 fmt [1:0] 10 digital audio interface format 00 = reserved 01 = left justified 10 = i2s format 11 = dsp/pcm mode r21 (15h) dac control 1 1 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted 0 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted r25 (19h) adc control 1 1 adcr_datinv 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted 0 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted table 45 audio data format control
production data WM8948 w pd, may 2011, rev 4.1 73 in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 23 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 24 i 2 s justified audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selected by lrclk_inv) following a rising edge of lrclk. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrclk output resembles the frame pulse shown in figure 25 and figure 26. in device slave mode, figure 27 and figure 28, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 25 dsp/pcm mode audio interface (mode a, lrclk_inv=0, master)
WM8948 production data w pd, may 2011, rev 4.1 74 figure 26 dsp/pcm mode audio interface (mode b, lrclk_inv=1, master) figure 27 dsp/pcm mode audio interface (mode a, lrclk_inv=0, slave) figure 28 dsp/pcm mode audio interface (mode b, lrclk_inv=0, slave) companding the WM8948 supports a-law and -law companding on both transmit (adc) and receive (dac) sides as shown in table 46. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. this provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization.
production data WM8948 w pd, may 2011, rev 4.1 75 register address bit label default description r5 (05h) companding control 3 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 2 dac_comp mode 0 dac companding mode 0 = -law 1 = a-law 1 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 0 adc_comp mode 0 adc companding mode 0 = -law 1 = a-law table 46 companding control companding uses a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) } for -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 29 -law companding
WM8948 production data w pd, may 2011, rev 4.1 76 a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 30 a-law companding the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). companded data is transmitted in the first 8 msbs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as shown in table 47. bit7 bit[6:4] bit[3:0] sign exponent mantissa table 47 8-bit companded word composition 8-bit mode is selected whenever dac_comp=1 or adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cycles per left/right clock frame. when using dsp mode b, 8-bit data words may be transferred consecutively every 8 bclk cycles. 8-bit mode (without companding) may be enabled by setting dac_compmode=1 or adc_compmode=1, when dac_comp=0 and adc_comp=0. loopback a loopback function is provided for test and evaluation purposes. when the loo pback register bit is set, the dac input data is fed through the dsp core to the adc output, as illustrated in figure 31.
production data WM8948 w pd, may 2011, rev 4.1 77 digital audio interface dacdat adcdat lrclk bclk adc r adc l dac r dac l audio interface loopback mode se1 (lpf/hpf, 3d-surround, 5-notch, df1) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control) figure 31 audio interface loopback register address bit label default description r5 (05h) companding control 5 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (dacdat input is fed through the dsp core to the adcdat output). table 48 loopback control digital pull-up and pull-down the WM8948 provides integrated pull-up and pull-down resistors on each of the dacdat, lrclk and bclk pins. this provides a flexible capability for interfacing with other devices. each of the pull- up and pull-down resistors can be configured independently using the register bits described in table 49.
WM8948 production data w pd, may 2011, rev 4.1 78 register address bit label default description r4 (04h) audio interface 15:14 dacdata_ pull [1:0] 00 dacdat pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 frame_pull [1:0] 00 lrclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 bclk_pull [1:0] 00 bclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved table 49 pull-up and pull-down control clocking and sample rates the internal clocks for the codec and digital audio interface are derived from a common internal clock source, sysclk. this clock can either be derived directly from mclk, or may be generated using the frequency locked loop (fll) using mclk as a reference. all commonly-used audio sample rates can be derived directly from typical mclk frequencies; the fll provides additional flexibility for a wider range of mclk frequencies. the WM8948 supports a wide range of standard audio sample rates from 8khz to 48khz. when the adc and dac are both enabled, they operate at the same sample rate, fs. other functions such as the auxadc, touch panel controller, interrupts, gpio input de-bounce and pga zero-cross timeouts are clocked using a free-running oscillator. the control registers associated with clocking and sample rates are described in table 50. the overall clocking scheme for the WM8948 is illustrated in figure 32. figure 32 WM8948 clocking overview
production data WM8948 w pd, may 2011, rev 4.1 79 sysclk may be derived either from mclk or from the fll; this is selected using the sysclk_src register bit. sysclk is enabled using the sysclk_ena and may be modified using a programmable divider configured by sysclk_div. it is important that sysclk_div is correctly set in order to produce 512 x fs at its output, where fs is the audio sampling rate. the sampling rate for the codec and digital audio interface is configured using the sr register field. in master mode, the frequency of the left/right clock output on the lrclk pin is the bclk frequency divided by 64 producing 32 bclk cycles per channel. in master mode, the bclk_div register configures the bit clock frequency output on bclk. the WM8948 can output a configurable clock on the gpio pins; this is enabled automatically whenever a gpio pin is configured for clkout output. the source can either be before or after the sysclk divider, as shown in figure 32. the source is selected using clkout_sel, and may be modified using a programmable divider configured by clkout_div. the WM8948 free-running oscillator required for auxadc, touch panel, gpio input de-bounced and interrupt functions must be enabled using osc_clk_ena whenever any of these functions is required. the zero-cross facility on input and output pgas requires a timeout clock. this is enabled using the toclk_ena bit. the oscillator must also be enabled using osc_clk_ena. register address bit label default description r6 (06h) clock gen control 15 osc_clk_ena 0 oscillator enable 0 = disabled 1 = enabled this needs to be set when doing auxadc measurements, or when a timeout clock is required for pga zero cross or gpio input detection 14:13 mclk_pull [1:0] 00 mclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 clkout_sel 0 clkout source select 0 = sysclk 1 = fll or mclk (set by sysclk_src register) 11:10 clkout_div [1:0] 00 clkout clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 sysclk_ena 0 sysclk e nable 0 = disabled 1 = enabled 8 sysclk_src 0 sysclk source select 0 = mclk 1 = fll output
WM8948 production data w pd, may 2011, rev 4.1 80 register address bit label default description 7:5 sysclk_div [2:0] 000 sysclk clock divider (sets the scaling for either the mclk or fll clock output, depending on sysclk_src) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 toclk_ena 0 toclk enabled (enables timeout clock for gpio level detection, amu, and pga zero cross timeout) 0 = disabled 1 = enabled r7 (07h) additional control 3:0 sr [3:0] 1101 audio sample rate select 0011 = 8khz 0100 = 11.025khz 0101 = 12khz 0111 = 16khz 1000 = 22.05khz 1001 = 24khz 1011 = 32khz 1100 = 44.1khz 1101 = 48khz table 50 clocking and sample rate control digital mic clocking when any gpio is configured as dmicclk output, the WM8948 outputs a clock which supports digital mic operation at the adc sampling rate. although the adc is not used, the sysclk and sample rate control fields must still be set as they would for adc operation. the clock frequencies for each of the sample rates is shown in table 51 pcm sample rate dmicclk fs rate 8khz 1.024mhz 128fs 11.025khz 1.411mhz 128fs 12khz 1.536mhz 128fs 16khz 2.048mhz 128fs 22.05khz 2.8224mhz 128fs 24khz 3.072mhz 128fs 32khz 2.048mhz 64fs 44.1khz 2.8224mhz 64fs 48khz 3.072mhz 64fs table 51 digital microphone clock frequencies
production data WM8948 w pd, may 2011, rev 4.1 81 frequency locked loop (fll) the integrated fll can be used to generate sysclk from a wide variety of different reference sources and frequencies. the fll uses mclk as its reference, which may be a high frequency (eg. 12.288mhz) or low frequency (eg. 32,768khz) reference. the fll is tolerant of jitter and may be used to generate a stable sysclk from a less st able input signal. the fll characteristics are summarised in ?electrical characteristics?. the fll is enabled using the fll_ena register bit. at initial power on the vmid voltage must be allowed to settle at its final vale before enabling the fll. note that, when changing fll settings, it is recommended that the digital circuit be disabled via fll_ena and then re-enabled after the other register settings have been updated. when changing the input reference frequency f ref , it is recommended that the fll be reset by setting fll_ena to 0. the field fll_clk_ref_div provides the option to divide the input reference (mclk) by 1, 2, 4 or 8. this field should be set to bring the reference down to 13.5mhz or below. for best performance, it is recommended that the highest possible frequency - within the 13.5mhz limit - should be selected. the field fll_ctrl_rate controls internal functions within the fll; it is recommended that only the default setting be used for this parameter. fll_gain controls the internal loop gain and should be set to the recommended value. the fll output frequency is directly determined from fll_fratio, fll_outdiv and the real number represented by fll_n and fll_k. the field fll_n is an integer (lsb = 1); fll_k is the fractional portion of the number (msb = 0.5). the fractional portion is only valid when enabled by the field fll_frac. power consumption in the fll is reduced in integer mode; however, the performance may also be reduced, with increased noise or jitter on the output. if low power consumption is required, then fll settings must be chosen where n.k is an integer (ie. fll_k = 0). in this case, the fractional mode can be disabled by setting fll_frac = 0. for best fll performance, a non-integer value of n.k is required. in this case, the fractional mode must be enabled by setting fll_frac = 1. the fll settings must be adjusted, if necessary, to produce a non-integer value of n.k. the fll output frequency is generated according to the following equation: f out = (f vco / fll_outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll_fratio) f ref is the input frequency, as determined by fll_clk_ref_div. f vco must be in the range 90-100 mhz. frequencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures.
WM8948 production data w pd, may 2011, rev 4.1 82 in order to follow the above requirements for f vco , the value of fll_outdiv should be selected according to the desired output f out , as described in table 52. output frequency f out fll_outdiv 2.8125 mhz - 3.125 mhz 4h (divide by 32) 5.625 mhz - 6.25 mhz 3h (divide by 16) 11.25 mhz - 12.5 mhz 2h (divide by 8) 22.5 mhz - 25 mhz 1h (divide by 4) 45 mhz - 50 mhz 0h (divide by 2) table 52 selection of fll_outdiv the value of fll_fratio should be selected as described in table 53. reference frequency f ref fll_fratio 1mhz - 13.5mhz 0h (divide by 1) 256khz - 1mhz 1h (divide by 2) 128khz - 256khz 2h (divide by 4) 16khz - 128khz 3h (divide by 8) less than 16khz 4h (divide by 16) table 53 selection of fll_fratio in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll_outdiv) the value of fll_n and fll_k can then be determined as follows: n.k = f vco / (fll_fratio x f ref ) note that f ref is the input frequency, after division by fll_clk_ref_div, where applicable. in fll fractional mode, the fractional portion of the n.k multiplier is held in the fll_k register field. this field is coded as a fixed point quantity, where the msb has a weighting of 0.5. note that, if desired, the value of this field may be calculated by multiplying k by 2^16 and treating fll_k as an integer value, as illustrated in the following example: if n.k = 8.192, then k = 0.192. multiplying k by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex). for best fll performance, the fll fractional mode is recommended. therefore, if the calculations yield an integer value of n.k, then it is recommended to adjust fll_fratio in order to obtain a non- integer value of n.k. care must always be taken to ensure that the fll operating frequency, f vco , is within its recommended limits of 90-100 mhz. the register fields that control the fll are described in table 54. example settings for a variety of reference frequencies and output frequencies are shown in table 55.
production data WM8948 w pd, may 2011, rev 4.1 83 register address bit label default description r8 (08h) fll control 1 12:11 fll_clk_ ref_div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 10:8 fll_outdiv [2:0] 001 f out clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 (f out = f vco / fll_outdiv) 7:5 fll_ctrl_ rate [2:0] 000 frequency of the fll control block 000 = f vco / 1 (recommended value) 001 = f vco / 2 010 = f vco / 3 011 = f vco / 4 100 = f vco / 5 101 = f vco / 6 110 = f vco / 7 111 = f vco / 8 recommended that this register is not changed from default. 4:2 fll_fratio [2:0] 000 f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 000 recommended for f ref > 1mhz 100 recommended for f ref < 16khz 011 recommended for all other cases 1 fll_frac 1 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non-integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled
WM8948 production data w pd, may 2011, rev 4.1 84 register address bit label default description r9 (09h) fll control 2 15:0 fll_k[15:0] 3137h fractional multiply for f ref (msb = 0.5) r10 (0ah) fll control 3 14:5 fll_n[9:0] 008h integer multiply for f ref (lsb = 1) 3:0 fll_gain [3:0] 0100 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that this register is set to 0000. table 54 frequency locked loop control example fll calculation to generate 24.576mhz output (f out ) from a 12.000mhz reference clock (f ref ): ? set fll_clk_ref_div in order to generate f ref <=13.5mhz: fll_clk_ref_div = 00 (divide by 1) ? set fll_ctrl_rate to the recommended setting: fll_ctrl_rate = 000 (divide by 1) ? sett fll_gain to the recommended setting: fll_gain = 0000 (multiply by 1) ? set fll_outdiv for the required output frequency as shown in table 52:- f out = 24.576mhz, therefore fll_outdiv = 1h (divide by 4) ? set fll_fratio for the given reference frequency as shown in table 53: f ref = 12mhz, therefore fll_fratio = 0h (divide by 1) ? calculate f vco as given by f vco = f out x fll_outdiv:- f vco = 24.576 x 4 = 98.304mhz ? calculate n.k as given by n.k = f vco / (fll_fratio x f ref ): n.k = 98.304 / (1 x 12) = 8.192 ? determine fll_n and fll_k from the integer and fractional portions of n.k:- fll_n is 8(dec) = 008(hex). fll_k is 0.192 (dec) = 3127(hex). ? confirm that n.k is a fractional quantity and set fll_frac: n.k is fractional. set fll_frac = 1. note that, if n.k is an integer, then an alternative value of fll_fratio may be selected in order to produce a fractional value of n.k.
production data WM8948 w pd, may 2011, rev 4.1 85 example fll settings table 55 provides example fll settings for generating common sysclk fr equencies from a variety of low and high frequency reference inputs. f ref f out fll_clk_ ref_div f vco fll_n fll_k fll_ fratio fll_ outdiv fll_ frac 8.000 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 705 (2c1h) 0.6 (9999h) 16 (4h) 4 (1h) 1 8.000 khz 24.576 mhz divide by 1 (0h) 98.304 mhz 768 (300h) 0.0 (0000h) 16 (4h) 4 (1h) 0 32.768 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 344 (158h) 0.53125 (8800h) 8 (3h) 4 (1h) 1 32.768 khz 24.576 mhz divide by 1 (0h) 98.304 mhz 375 (177h) 0.0 (0000h) 8 (3h) 4 (1h) 0 768.000 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 14 (00eh) 0.7 (b333h) 8 (3h) 4 (1h) 1 768.000 khz 24.576 mhz divide by 1 (0h) 98.304 mhz 16 (010h) 0.0 (0000h) 8 (3h) 4 (1h) 0 1.024 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 88 (058h) 0.2 (3333h) 1 (0h) 4 (1h) 1 1.024 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 96 (060h) 0.0 (0000h) 1 (0h) 4 (1h) 0 6.144 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 14 (00eh) 0.7 (b333h) 1 (0h) 4 (1h) 1 6.144 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 16 (010h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.70749 (b51eh) 1 (0h) 4 (1h) 1 12.000 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.5264 (86c2h) 1 (0h) 4 (1h) 1 12.000 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.192 (3127h) 1 (0h) 4 (1h) 1 12.288 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.35 (599ah) 1 (0h) 4 (1h) 1 12.288 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 13.000 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 6 (006h) 0.94745 (f28ch) 1 (0h) 4 (1h) 1 13.000 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 7 (007h) 0.56185 (8fd5h) 1 (0h) 4 (1h) 1 19.200 mhz 22.5792 mhz divide by 2 (1h) 90.3168 mhz 9 (009h) 0.408 (6873h) 1 (0h) 4 (1h) 1 19.200 mhz 24.576 mhz divide by 2 (1h) 98.304 mhz 10 (00ah) 0.24 (3d71h) 1 (0h) 4 (1h) 1 27.000 mhz 22.5792 mhz divide by 2 (1h) 90.3168 mhz 6 (006h) 0.69013 (b0adh) 1 (0h) 4 (1h) 1 27.000 mhz 24.576 mhz divide by 2 (1h) 98.304 mhz 7 (007h) 0.28178 (4823h) 1 (0h) 4 (1h) 1 table 55 example fll settings
WM8948 production data w pd, may 2011, rev 4.1 86 video buffer the WM8948 provides a current mode output video buffer with an input 3 rd order butterworth low pass filter (lpf) and clamp. the video buffer is powered from ldovdd - typically 3.3v. the video buffer is compatible with pal and ntsc video formats. the low pass filter (lpf) is intended to remove images in the video dac output waveform at multiples of the dac clock frequency. the input clamp supports ac coupling at the input to the video buffer. figure 33 video buffer lowpass filt er frequency response gain=0db the current mode output employed by the WM8948 video buffer allows operation at lower supply voltages than voltage mode video buffers. the current mode output also provides inherent protection against short circuits during jack insertion and removal. a current reference resistor (positioned close to the WM8948) ensures that the signal swing at the output of the buffer is the same as that at the receiving equipment (e.g. a television set), thus providing excellent signal reproduction. for best performance, the input to the video buffer should be ac coupled and terminated to 75 . note that the input clamp and pull-down features described below are only applicable to the ac- coupled input configuration. care should be taken with pcb layout, designing for at least 1ghz frequencies to avoid degrading performance. pcb vias and sharp corners should be avoided and parasitic capacitance minimised on signal paths; these should be kept as short and straight as possible. the ldovdd supply should be decoupled as close to the WM8948 as possible. see the ?external components? section for more information. the video buffer is enabled using the vb_ena register bit. the gain of the video buffer is selected using vb_gain; this can be set to 0db or 6db (corresponding to 6db or 12db unloaded). the lpf response can be adjusted by setting the vb_qboost register; this provides a small amount of additional gain in the region of the cut-off frequency. the input signal clamp is enabled using vb_clamp; this controls the dc component of the video signal for compatibility with the WM8948. the video buffer pull-down can be enabled using vb_pd; this may be used during power-up of the video buffer in order to align the signal levels between the source and the WM8948. note that the pull-down should not be enabled during normal operation of the video buffer; it should be enabled when the video buffer is first powered up, and subsequently disabled (eg. after 20ms) once the circuit has settled. a programmable dc offset can be applied to the output signal using the vb_disoff register field; this can be set to 0mv, 20mv or 40mv offset. note that the vmid reference (see ?voltage references and master bias?) must be enabled when using the WM8948 video buffer. vmid is enabled by setting vmid_ena, as defined in table 40.
production data WM8948 w pd, may 2011, rev 4.1 87 the video buffer control registers are described in table 56. register address bit label default description r38 (26h) video buffer 7 vb_ena 0 video buffer enable 0 = disabled 1 = enabled 6 vb_qboost 0 video buffer filter q-boost control 0 = disabled 1 = enabled 5 vb_gain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = 6db (=12db unloaded) 4:3 vb_disoff 111 video buffer dc offset control 000 = reserved 001 = 40mv offset 010 = reserved 011 = 20mv offset 100 = reserved 101 = reserved 110 = reserved 111 = 0mv offset note - the specified offset applies to the 0db gain setting (vb_gain=0). when 6db gain is selected, the dc offset is doubled. 1 vb_pd 0 video buffer pull-down 0 = pull-down disabled 1 = pull-down enabled 0 vb_clamp 0 enable the clamp between the video input and ground 0 = no clamp 1 = video buffer input is clamped to ground table 56 video buffer control the video buffer circuit is illustrated in figure 34. figure 34 video buffer block diagram the video buffer requires two external resistor components, as illustrated in figure 34. for best performance, the resistor r source should be matched (equal) to the load impedance r load .
WM8948 production data w pd, may 2011, rev 4.1 88 the resistance r ref is a function of the circuit gain and a function of the parallel combination of r source and rl oad . when vb_gain = 0 (0db gain), the current gain of the video buffer is 5, as described by the equation i vbout = 5 x i vbref . the resistor r ref should be set equal to 5 x (r source // r load ), where (r source // r load ) is the effective resistance of the parallel combination of r source and r load . (note that the required resistance r ref is the same for both settings of vb_gain.) in a typical application, r load = 75 , r source = 75 , r ref = 187 . recommended video buffer initialisation sequence power up (video signal ac coupled to video buffer input): action label register[bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) sw_reset r0 (00h) [15:0] enable vmid fast start and start up bias select start-up bias and set vmid soft start for start-up ramp vmid_fast_start = 1 startup_bias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the reference voltage for the ldo then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ldo start-up bias and enable ldo delay 300ms for ldo to settle ldo_ref_sel_fast = 1 ldo_bias_src = 1 ldo_ena = 1 r53 (35h) [14] r53 (35h) [5] r53 (35h) [15] enable vmid buffer and master bias set vmid_sel[1:0] for fast start-up bias_ena = 1 vmid_buf_ena = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] enable vmid delay 150ms to allow vmid to settle vmid_ena = 1 r7 (07h) [4] set ldo for normal operation ldo_ref_sel_fast = 0 ldo_bias_src = 0 r53 (35h) [14] r53 (35h) [5] set vmid for normal operation vmid_fast_start = 0 startup_bias_ena = 0 r7 (07h) [11] r7 (07h) [8] set vmid divider for normal operation vmid_sel = 01 r2 (02h) [1:0] enable vmid delay 150ms to allow vmid to settle vmid_ena = 1 r7 (07h) [4] set ldo for normal operation ldo_ref_sel_fast = 0 ldo_bias_src = 0 r53 (35h) [14] r53 (35h) [5] set video buffer gain as required vb_gain r38 (26h) [5] set video buffer filter q boost as required vb_qboost r38 (26h) [6] enable video buffer clamp vb_clamp = 1 r38 (26h) [0] enable video buffer pulldown vb_pd = 1 r38 (26h) [1] enable video buffer vb_ena = 1 r38 (26h) [7] delay 20ms for buffer to capture input level disable video buffer pulldown vb_pd = 0 r38 (26h) [1]
production data WM8948 w pd, may 2011, rev 4.1 89 power up (video signal dc coupled to video buffer input): action label register[bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) sw_reset r0 (00h) [15:0] enable vmid fast start and start up bias select start-up bias and set vmid soft start for start-up ramp vmid_fast_start = 1 startup_bias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the reference voltage for the ldo then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ldo start-up bias and enable ldo delay 300ms for ldo to settle ldo_ref_sel_fast = 1 ldo_bias_src = 1 ldo_ena = 1 r53 (35h) [14] r53 (35h) [5] r53 (35h) [15] enable vmid buffer and master bias set vmid_sel[1:0] for fast start-up bias_ena = 1 vmid_buf_ena = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] enable vmid delay 150ms to allow vmid to settle vmid_ena = 1 r7 (07h) [4] set ldo for normal operation ldo_ref_sel_fast = 0 ldo_bias_src = 0 r53 (35h) [14] r53 (35h) [5] set vmid for normal operation vmid_fast_start = 0 startup_bias_ena = 0 r7 (07h) [11] r7 (07h) [8] set vmid divider for normal operation vmid_sel = 01 r2 (02h) [1:0] set video buffer gain as required vb_gain r38 (26h) [5] set video buffer filter q boost as required vb_qboost r38 (26h) [6] enable video buffer vb_ena = 1 r38 (26h) [7]
WM8948 production data w pd, may 2011, rev 4.1 90 auxiliary adc the WM8948 incorporates a low-power 12-bit auxiliary adc (auxadc). this can be used to measure the spkvdd supply voltage and to measure other analogue voltages connected to the aux1 or aux2 inputs. the auxiliary adc is powered from ldovdd - typically 3.3v. the auxadc is also used to perform touch panel measurements; these are interleaved with the auxadc measurement requests; see ?touch panel controller? for further details. the auxadc is powered on the tpvdd (internal) power domain; internal resistor dividers enable spkvdd voltages greater tpvdd to be measured by the auxadc. auxadc control the auxadc is enabled by setting the aux_ena register bit. the auxadc measurements can be initiated manually or automatically. for automatic operation, the aux_rate register is set according to the required conversion rate, and conversions are enabled by setting the aux_cvt_ena bit. for manual operation, the aux_rate register is set to 00h, and each manual conversion is initiated by setting the aux_cvt_ena bit. in manual mode, the aux_cvt_ena bit is reset by the WM8948 after each conversion request. the auxadc has 3 available input sources, which are spkvdd, aux1 and aux2. each of these inputs is enabled by setting the respective bit in the auxadc source register (r62). the WM8948 provides options to select the scaling and voltage reference for these inputs; these are described in table 58. note that the aux1 and aux2 pins should not be used as auxadc inputs if they are used as audio inputs. (see ?input signal path?.) for each auxadc measurement event (in manual or automatic modes), the WM8948 selects the next enabled input source. any number of inputs may be selected simultaneously; the auxadc will measure each on in turn. note that only a single auxadc measurement is made on any manual or automatic trigger. the control fields associated with initiating auxadc measurements are defined in table 57. register address bit label default description r61 (3dh) auxadc control 15 aux_ena 0 auxadc enable 0 = disabled 1 = enabled 14 aux_cvt_ena 0 auxadc conversion enable 0 = disabled 1 = enabled in automatic mode, conversions are enabled by setting this bit. in manual mode (aux_rate = 0), setting this bit will initiate a conversion; the bit is reset automatically. 4:0 aux_rate [4:0] 0_0000 auxadc conversion rate 0_0000 = manual conversion 0_0001 = 16hz 0_0010 = 32hz ?(16hz steps) 1_1111 = 496hz r62 (3eh) auxadc source 8 aux_batt_sel 0 auxadc battery (spkvdd) input select 0 = disable battery (spkvdd) measurement 1 = enable battery (s pkvdd) measurement
production data WM8948 w pd, may 2011, rev 4.1 91 register address bit label default description 1 aux_aux2_sel 0 auxadc aux2 input select 0 = disable aux2 measurement 1 = enable aux2 measurement 0 aux_aux1_sel 0 auxadc aux1 input select 0 = disable aux1 measurement 1 = enable aux1 measurement table 57 auxadc control auxadc input configuration for inputs aux1 and aux2, the auxadc uses either ldovdd/2 or the 1.5v (nominal) bandgap as a reference. this is selected independently for each aux input, as described in table 58. selecting the bandgap as a reference provides additional immunity to any noise on the supply rails. the internal bandgap reference is nominally 1.5v. note that this value is not trimmed and may vary significantly (+/-10%) between different devices. when using this reference, the internal bandgap reference must be enabled by setting the bg_ena register, as described in table 58. for spkvdd measurement, the spkvdd volt age is connected to a potential divider in order to reduce it to a suitable level. two different scaling factors are available, controlled by the aux_batt_scale register bit. the scaling factor should be selected such that the scaled output is less than the maximum measurable level (ldovdd). for optimum measurement of the spkvdd voltage, the spkvdd potential divider can be c onnected to the aux1 pin, allowing an external capacitor to be used to filter noise from the spkvdd supply. this is enabled by setting the aux_aux1_filtb register bit. this option can only be used when aux1 is not also used as an input to the auxadc. register address bit label default description r54 (36h) bandgap 15 bg_ena 0 bandgap reference control 0 = disabled 1 = enabled r63 (3fh) auxadc config 9 aux_aux1_ filtb 0 auxadc battery (spkvdd) measurement filter control 0 = disabled 1 = enabled when aux_aux1_filtb is set, the battery (spkvdd) measurement point is connected to the aux1 pin, allowing an external capacitor to be used to filter noise. 8 aux_batt_ scale 1 auxadc battery (spkvdd) measurement divider control 0 = 0.45 x spkvdd (note that 0.45 x 3.3v = 1.485v) 1 = 0.41 x spkvdd (note that 0.41 x 3.6v = 1.476v) 1 aux_aux2_ ref 0 auxadc aux2 reference select 0 = ldovdd/2 1 = 1.5v (nominal) bandgap 0 aux_aux1_ ref 0 auxadc aux1 reference select 0 = ldovdd/2 1 = 1.5v (nominal) bandgap table 58 auxadc input configuration
WM8948 production data w pd, may 2011, rev 4.1 92 auxadc readback measured data from the auxadc is read via the auxadc data register (r60), which contains two fields. the auxadc data source is indicated in the aux_data_src field; the associated measurement data is contained in the aux_data field. reading from the auxadc data register returns a 12-bit code which represents the most recent auxadc measurement on the associated channel. it should be noted that every time an auxadc measurement is written to the auxadc data register, the previous data is overwritten - the host processor should ensure that data is read from this register before it is overwritten. the 12-bit aux_data field can be equated to the actual voltage by scaling according to the applicable reference source. the full-scale value of aux_data corresponds to the ldovdd voltage level. the auxadc interrupts can be used to indicate when new data is available - see ?interrupts?. a gpio pin configured as ?aux_done? can also be used to indicate when new data is available - see ?general purpose input / output?. in a typical application, it is anticipated that the auxadc interrupt or gpio flag would be used to control the auxadc readback - the host processor should read the auxadc data register in response to the auxadc event. in automatic auxadc mode, the processor should complete this action before the next measurement occurs, in order to avoid losing any auxadc samples. in manual conversion mode, the interrupt signal provides confirmation that the commanded measurement has been completed. the control fields associated with auxadc readback are defined in table 59. register address bit label default description r60 (3ch) aux adc data 13:12 aux_data_ src [1:0] 00 auxadc data source 00 = no measurement 01 = aux1 10 = aux2 11 = spkvdd 11:0 aux_data [11:0] 000h auxadc data (12 bit unsigned data) table 59 auxadc readback
production data WM8948 w pd, may 2011, rev 4.1 93 touch panel controller the WM8948 incorporates a touch panel controller interface, for use with standard 4-wire touch panels. the controller supports x, y co-ordinate measurement, pen down detection and touch pressure (z-axis) measurement. the touch panel controller provides high resolution digitiser measurements, using the same 12-bit auxadc as described earlier (see ?auxiliary adc?). touch panel conversion requests are interleaved with auxadc measurement requests. touch panel interrupts can be generated on completion of a set of measurements, or on pen down detection. read access to the touch panel measurement data is controlled in order to ensure the host always reads a complete set of data, and does not read mixed data that relates to separate measurement events. an overview of touch panel operating principles is provided at the end of this section. touch panel control the touch panel is enabled by setting the tch_ena register bit. the touch panel measurements can be initiated manually or automatically. for automatic operation, the tch_rate register is set according to the required conversion rate, and measurements are enabled by setting the tch_cvt_ena bit. for manual operation, the tch_rate register is set to 00h, and a set of measurements is initiated by setting the tch_cvt_ena bit. in manual mode, the tch_cvt_ena bit is reset by the WM8948 after each conversion request. the touch panel ?pen down? detection can be used to control measurements in automatic mode. when tch_pdonly is set, then automatic conversions will only be scheduled when ?pen down? is detected. note that manual conversion commands are not affected by tch_pdonly. for each touch panel measurement event (in manual or automatic modes), the WM8948 performs a set of measurements encompassing all enabled input sources; the x-axis, y-axis and z-axis measurements are enabled using the tch_x_ena, tch_y_ena and tch_z_ena register bits respectively. to allow settling time between consecutive measurements, a programmable delay is applied between the x, y and z-axis measurements; this is set using the tch_delay field. pressure measurement uses a constant current source to measure the resistance between the top and bottom sheets of the touch panel. the current is selectable using tch_isel, to suit different types of touch panel. pen down detection sensitivity can be controlled using tch_rpu. decreasing the resistance makes the touch panel less sensitive; increasing the resistance makes the touch panel more sensitive. the control fields associated with initiating touch panel measurements are defined in table 60. register address bit label default description r55 (37h) touch control 1 15 tch_ena 0 touch panel enable 0 = disabled 1 = enabled 14 tch_cvt_ena 0 touch panel conversion enable 0 = disabled 1 = enabled in automatic mode, conversions are enabled by setting this bit. in manual mode (tch_rate = 0), setting this bit will initiate a set of conversion; the bit is reset automatically. 10 tch_z_ena 0 enables z-axis touch panel measurements. 0 = disabled 1 = enabled
WM8948 production data w pd, may 2011, rev 4.1 94 register address bit label default description 9 tch_y_ena 0 enables y-axis touch panel measurements 0 = disabled 1 = enabled 8 tch_x_ena 0 enables x-axis touch panel measurements 0 = disabled 1 = enabled 7:5 tch_delay [2:0] 000 settling time between x, y and z measurements. (nominal timing only; typically +/-20% of quoted values.) 000 = 30us 001 = 60us 010 = 120us 011 = 240us 100 = 480us 101 = 960us 110 = 1920us 111 = 3840us 4:0 tch_rate [4:0] 0_0000 touch panel rate 0_0000 = manual conversion 0_0001 = 16khz 0_0010 = 32khz ?(16khz steps) 1_1111 = 496khz r56 (38h) touch control 2 11 tch_pdonly 0 select automatic conversions only when pen down is detected. (no effect on manual conversion.) 0 = normal 1 = pen-down only 8 tch_isel 0 pressure measurement current select 0 = 230ua 1 = 460ua 3:0 tch_rpu [3:0] 0111 pen-down sensitivity (pull-up resistor) 0000 = 64k (most sensitive) 0001 = 64k / 2 0010 = 64k / 3 0011 = 64k / 4 ?. 1111 = 64k / 16 (least sensitive) table 60 touch panel control touch panel readback measured data from the touch panel controller is read via the touch data registers. the x-axis, y- axis and z-axis (pressure) measurements are provided in the tch_x, tch_y and tch_z registers respectively. the tch_pd1, tch_pd2 and tch_pd3 bits indicate whether the pen down status was asserted when the measurement set was made. to read a set of touch panel measurements, the host processor must access each of the applicable touch data registers. when the host processor starts to read these registers, the WM8948 will inhibit any new touch panel measurements until the host processor has read all of the applicable registers. this ensures that the data read by the host processor all relates to the same set of measurements.
production data WM8948 w pd, may 2011, rev 4.1 95 if all 3 touch panel channels are selected (using tch_x_ena, tch_y_ena and tch_z_ena) then all 3 touch data registers must be read before further measurements are permitted. if fewer channels are selected, then only those selected channels need to be read before touch panel measurements are enabled again. the touch panel inhibit (preventing new touch panel measurements) commences when any of the touch data registers is read. the touch panel inhibit ceases when all selected touch data registers have been read. the touch panel interrupts can be used to indicate when new data is available or if ?pen down? is detected - see ?interrupts?. a gpio pin configured as ?tch_done? or ?pdown? can also be used to indicate these events - see ?general purpose input / output?. the control fields associated with touch panel readback are defined in table 61. register address bit label default description r57 (39h) touch data x 15 tch_pd1 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_x [11:0] 000h touch panel x-axis data r58 (3ah) touch data y 15 tch_pd2 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_y [11:0] 000h touch panel y-axis data r59 (3bh) touch data z 15 tch_pd3 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_z [11:0] 000h touch panel z-axis data table 61 touch panel readback touch panel operating principles a typical touch panel comprises two conductive sheets, connected via a switch matrix to the touch panel supply voltage. when the touch panel is touched (usually with a pen-style pointer), an electrical contact is made between the two sheets. the switch matrix is used to determine the position of the pen contact by establishing a potential divider on one of the conductive sheets in either the x-axis or y-axis, and measuring the voltage on the other sheet. separate configuration is required for each axis measurement; these are configured one after the other to determine the x and y co-ordinate positions. note that, due to the ratiometric measurement method, the supply voltage does not affect the measurement accuracy in either axis. pen down detection and z-axis (pressure) measurements are achieved in a similar fashion, by configuring the switch matrix and taking the appropriate voltage measurement via an adc. the touch panel interface connects to the left / right sides of one sheet and to the top / bottom sides of the other sheet. the illustrations show the top sheet for x-axis and the bottom sheet for y- axis, but the reverse is also possible. x-axis measurement is performed by applying a potential difference between the left and right sides of the touch panel. when contact is made between the two sheets, the voltage present on the top or bottom connections is a measure of the x-axis position of the contact. the configuration is illustrated in figure 35.
WM8948 production data w pd, may 2011, rev 4.1 96 WM8948 yp xp yn xn gnd ldovdd aux adc x position figure 35 x-axis touch panel measurement y-axis measurement is performed by applying a potential difference between the top and bottom sides of the touch panel. when contact is made between the two sheets, the voltage present on the left or right connections is a measure of the y-axis position of the contact. the configuration is illustrated in figure 36. WM8948 yp xp yn xn gnd ldovdd aux adc y position figure 36 y-axis touch panel measurement ?pen down? detection uses a zero-power comparator with an internal, programmable pull-up resistor. when the touch panel is not being touched, no current flows between the touch panel sheets, and the comparator output is low. when the touch panel is touched, current flows through the panel and through the pull-up resistor, and the comparator output goes high. the sensitivity of the circuit can be adjusted using different values of pull-up resistor; a large pull-up resistance leads to the most sensitive response. the configuration is illustrated in figure 37. WM8948 yp xp yn xn gnd ldovdd r pu zero power comparator pen_down figure 37 pen-down touch panel detection
production data WM8948 w pd, may 2011, rev 4.1 97 touch pressure can only be determined indirectly, using the results of two separate measurements. a constant current is applied through the plates, and the voltage on each plate is measured. the difference between the two voltages is proportional to the resistance between the plates, which is a measure of the pressure being applied to the panel. the configuration is illustrated in figure 38. in this example, a constant current flows from the top (yp) connection to the left (xn) connection. the right (xp) and bottom (yn) points are measured in turn, and the difference, v x - v y is equal to i p x r c , where i p is the current applied and r c is the resistance between the plates. the smaller the measured resistance, the greater the pressure being applied. WM8948 yp xp yn xn gnd ldovdd aux adc pressure figure 38 z-axis (pressure) touch panel measurement general purpose input/output the WM8948 provides four multi-function pins which can be configured to provide a number of different functions. these are digital input/output pins on the dbvdd power domain. the gpio pins are: ? gpio1 ? cs /gpio2 ? cifmode/gpio3 ? sdout/gpio4 note that only gpio1 is a dedicated gpio pin; the other pins are shared with control interface functions. the pins available for gpio function depend on the selected control interface mode, as described in table 62. control interface mode gpio pin availability 2-wire (i2c) gpio1 gpio2 gpio3 gpio4 3-wire (spi) gpio1 gpio3 gpio4 4-wire (spi) gpio1 gpio3 table 62 gpio pin availability note that cifmode/gpio3 pin selects between i2c and spi control interface modes (see ?control interface?). to enable gpio functions on gpio3, the mode_gpio register bit must be set in order to disconnect this pin from the control interface circuit. setting the mode_gpio register bit causes the control interface mode selection to be latched; it will remain latched until a software reset or power on reset occurs. the register fields that control the gpio pins are described in table 63. for each gpio, the selected function is determined by the gpn_fn field, where n identifies the gpio pin (1 to 4). the pin direction, set by gpn_dir, must be set according to function selected by gpn_sel.
WM8948 production data w pd, may 2011, rev 4.1 98 when a pin is configured as a gpio output, its level can be set to logic 0 or logic 1 using the gpn_lvl field. when a pin is configured as a gpio input, the logic level can be read from the respective gpn_lvl bit. the gpio output is inverted with respect to the gpn_lvl register when the polarity bit gpn_pol is set; the equivalent is true of gpio inputs also. internal pull-up and pull-down resistors may be enabled using the gpn_pull fields; this allows greater flexibility to interface with different signals from other devices. each of the gpio pins is an input to the interrupt control circuit and can be used to trigger an interrupt event. this may be configured as level-triggered or edge-triggered using the gpn_fn registers. edge detect raises an interrupt when the gpio status changes; level detect asserts the interrupt for as long as the gpio status is asserted. see ?interrupts?. an edge-triggered gpio can be configured to trigger on a single edge or on both edges of the input signal; this is selected using the gpn_int_mode registers. a level-triggered or single-edge- triggered input may be configured using the gpn_pol registers to respond to a high level/edge (when gpn_pol = 0) or a low level/edge (when gpn_pol = 1). the gpio control fields are defined in table 61. register address bit label default description r11 (0bh) gpio config 0 gpio_mode 0 cifmode/gpio3 pin configuration 0 = pin configured as cifmode 1 = pin configured as gpio3 note - when this bit is set to 1, it is latched and cannot be reset until power-off or software reset. r12 (0ch) gpio1 control 15 gp1_dir 1 gpio1 pin direction 0 = output 1 = input 14:13 gp1_pull [1:0] 00 gpio1 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp1_int_ mode 0 gpio1 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp1_pol=0) or falling edge triggered (if gp1_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp1_pol 0 gpio1 polarity select 0 = non-inverted 1 = inverted 5 gp1_lvl 0 gpio1 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp1_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp1_fn [3:0] 0000 gpio1 pin function (see table 64 for details) r13 (0dh) gpio2 control 15 gp2_dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2_pull [1:0] 00 gpio2 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved
production data WM8948 w pd, may 2011, rev 4.1 99 register address bit label default description 12 gp2_int_ mode 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2_pol=0) or falling edge triggered (if gp2_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp2_pol 0 gpio2 polarity select 0 = non-inverted 1 = inverted 5 gp2_lvl 0 gpio2 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp2_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp2_fn [3:0] 0000 gpio2 pin function (see table 64 for details) r14 (0eh) gpio3 control 15 gp3_dir 1 gpio3 pin direction 0 = output 1 = input 14:13 gp3_pull [1:0] 10 gpio3 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp3_int_ mode 0 gpio3 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp3_pol=0) or falling edge triggered (if gp3_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp3_pol 0 gpio3 polarity select 0 = non-inverted 1 = inverted 5 gp3_lvl 0 gpio3 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp3_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp3_fn [3:0] 0000 gpio3 pin function (see table 64 for details) r15 (0fh) gpio4 control 15 gp4_dir 1 gpio4 pin direction 0 = output 1 = input 14:13 gp4_pull [1:0] 00 gpio4 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp4_int_ mode 0 gpio4 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp4_pol=0) or falling edge triggered (if gp4_pol =1) 1 = gpio interrupt is triggered on rising and falling edges
WM8948 production data w pd, may 2011, rev 4.1 100 register address bit label default description 10 gp4_pol 0 gpio4 polarity select 0 = non-inverted 1 = inverted 5 gp4_lvl 0 gpio4 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp4_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp4_fn [3:0] 0000 gpio4 pin function (see table 64 for details) table 63 gpio control gpio function select the available gpio functions are described in table 64. the function of each gpio is set using the gpn_fn register, where n identifies the gpio pin (1 to 4). note that the polarity of the gpio inputs and outputs may be selected using the gpn_pol register bits. when gpn_pol = 1, then the polarity is inverted with respect to the descriptions below. the gpio input functions may be used to detect headphone jack insertion or a button press. these signals may be used as inputs to the interrupt controller, via the integrated de-bounce circuit. gpn_fn description comments 0000 logic level input external logic level is read from gpn_lvl. associated interrupt (when enabled) is level-triggered. 0001 edge detection input external logic level is read from gpn_lvl. associated interrupt (when enabled) is edge triggered. note that toclk_ena must be set. 0010 clkout output output clock frequency is set by clkout_div. 0011 interrupt (irq) output hardware output of all unmasked interrupts. 0100 pen down output indicates touch panel pen down detection. this flag is asserted whenever the pen is in contact with the touch panel. 0101 touch panel measurement complete indicates a set of touch panel measurements has been completed. this function provides a pulse when new touch panel measurement data is ready. the pulse duration is approximately 1.95 s. 0110 auxiliary adc measurement complete indicates a new auxiliary adc measurement has been completed. this function provides a pulse when new auxadc measurement data is ready. the pulse duration is approximately 1.95 s. 0111 temperature flag output indicates the temperature sensor output. this is a hardware output of the temp_sts bit (assuming gpn_pol = 0). 0 = normal 1 = overtemperature 1000 reserved 1001 dmicclk output output clock for digital microphone interface 1010 logic level output pin logic level is set by gpn_lvl. 1011 ldo_uv output indicates the ldo undervoltage status. this is a hardware output of the ldo_uv_sts bit (assuming gpn_pol = 0). 0 = normal 1 = ldo undervoltage
production data WM8948 w pd, may 2011, rev 4.1 101 gpn_fn description comments 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 64 gpio function select interrupts the interrupt controller has multiple inputs. these include the gpio input pins, temperature sensor, auxiliary adc, touch panel and the ldo regulator. any combination of these inputs can be used to trigger an interrupt (irq) event. there is an interrupt status field associated with each of the irq inputs. these are listed within the system interrupts register (r16), as described in table 65. the status of the irq inputs can be read at any time from this register or else in response to the interrupt (irq) output being signalled via a gpio pin. individual mask bits can select or deselect different functions from the interrupt controller. these are listed within the system interrupts mask register (r19), as described in table 65. note that the status fields remain valid, even when masked, but the masked bits will not cause the interrupt (irq) output to be asserted. the interrupt (irq) output represents the logical ?or? of all the unmasked irq inputs. the bits within the system interrupts register (r16) are latching fields and, once they are set, they are not reset until the system interrupts register is read. accordingly, the interrupt (irq) output is not reset until the system interrupts register has been read. note that, if the condition that caused the irq input to be asserted is still valid, then the interrupt (irq) output will remain set even after the system interrupts register has been read. when gpio input is used to trigger an interrupt event, polarity can be set using the gpn_pol bits as described in table 63. this allows the irq event to be used to indicate a rising or a falling edge of the external logic signal. if desired, the gpn_int_mode bits can be used to select an interrupt event on both the rising and falling edges. the gpio inputs to the interrupt controller are de-bounced to avoid false detections. the timeout clock (toclk) is required for this function. when using gpio inputs to the interrupt controller, the toclk must be enabled by setting the toclk_ena and osc_clk_ena bits as described in ?clocking and sample rates?. the interrupt (irq) output can be globally masked by setting the im_irq register. the interrupt is masked by default. the interrupt (irq) output may be configured on any of the gpio pins. see ?general purpose input / output? for details of how to configure gpio pins for interrupt (irq) output. the interrupt control fields are defined in table 65.
WM8948 production data w pd, may 2011, rev 4.1 102 register address bit label default description r16 (10h) system interrupts 15 temp_int 0 thermal interrupt status 0 = thermal interrupt not set 1 = thermal interrupt set this bit is latched when set; it is cleared when the register is read. 14 gp4_int 0 gpio4 interrupt status 0 = gpio4 interrupt not set 1 = gpio4 interrupt set this bit is latched when set; it is cleared when the register is read. 13 gp3_int 0 gpio3 interrupt status 0 = gpio3 interrupt not set 1 = gpio3 interrupt set this bit is latched when set; it is cleared when the register is read. 12 gp2_int 0 gpio2 interrupt status 0 = gpio2 interrupt not set 1 = gpio2 interrupt set this bit is latched when set; it is cleared when the register is read. 11 gp1_int 0 gpio1 interrupt status 0 = gpio1 interrupt not set 1 = gpio1 interrupt set this bit is latched when set; it is cleared when the register is read. 10 tchdata_int 0 touch panel data ready interrupt 0 = touch panel data ready interrupt not set 1 = touch panel data ready interrupt set this bit is latched when set; it is cleared when the register is read. 9 tchpd_int 0 touch panel pen down interrupt 0 = touch panel pen down interrupt not set 1 = touch panel pen down interrupt set this bit is latched when set; it is cleared when the register is read. 8 auxadc_int 0 auxadc data ready interrupt 0 = auxadc data ready interrupt not set 1 = auxadc data ready interrupt set this bit is latched when set; it is cleared when the register is read. 0 ldo_uv_int 0 ldo undervoltage interrupt 0 = ldo undervoltage interrupt not set 1 = ldo undervoltage interrupt set this bit is latched when set; it is cleared when the register is read. r18 (12h) irq config 0 im_irq 1 irq (gpio output) mask 0 = normal 1 = irq output is masked
production data WM8948 w pd, may 2011, rev 4.1 103 register address bit label default description r19 (13h) system interrupts mask 15 im_temp_int 0 interrupt mask for thermal status 0 = not masked 1 = masked 14 im_gp4_int 0 interrupt mask for gpio4 0 = not masked 1 = masked 13 im_gp3_int 0 interrupt mask for gpio3 0 = not masked 1 = masked 12 im_gp2_int 0 interrupt mask for gpio2 0 = not masked 1 = masked 11 im_gp1_int 0 interrupt mask for gpio1 0 = not masked 1 = masked 10 im_tchdata_ int 0 interrupt mask for touch panel data ready status 0 = not masked 1 = masked 9 im_tchpd_int 0 interrupt mask for touch panel pen down status 0 = not masked 1 = masked 8 im_auxadc_ int 0 interrupt mask for auxadc data ready status 0 = not masked 1 = masked 0 im_ldo_uv_ int 0 interrupt mask for ldo undervoltage status 0 = not masked 1 = masked table 65 interrupt control control interface the WM8948 is controlled by writing to its control registers. readback is available for all registers. the control interface can operate as either a 2-, 3- or 4-wire interface: ? 2-wire (i2c) mode uses pins sclk and sda ? 3-wire (spi) mode uses pins cs , sclk and sda ? 4-wire (spi) mode uses pins cs , sclk, sda and sdout readback is provided on the bi-directional pin sda in 2-/3-wire modes. the device address in 2-wire (i2c) mode is 34h. the WM8948 uses 15-bit register addresses and 16-bit data in all control interface modes.
WM8948 production data w pd, may 2011, rev 4.1 104 selection of control interface mode the WM8948 control interface can be configured for i2c mode or spi modes using the cifmode/gpio3 pin at power-up. the mode selection is as described in table 67. cifmode/gpio3 interface format low 2 wire high 3- or 4- wire table 66 control interface mode selection after the control interface mode has been configured, the mode_gpio register bit should be set in order to latch the selection and to allow gpio functions to be supported on the cifmode/gpio3 pin. after the mode_gpio register bit has been set, the control interface mode selection will remain latched until a software reset or power on reset occurs. see ?general purpose input / output? for details. in 2-wire (i2c) control interface mode, auto-increment mode may be selected. this enables multiple write and multiple read operations to be scheduled faster than is possible with single register operations. the auto-increment option is enabled when the auto_inc register bit is set. this bit is defined in table 67. auto-increment is disabled by default. in spi modes, 3-wire or 4-wire operation may be selected using the spi_4wire register bit. in 3-wire mode, register readback is provided using the bi-directional pin sda. in 4-wire mode, register readback is provided using sdout. the sdout pin may be configured as cmos or as open drain using the spi_od bit. in 3-wire mode the sda pin may be configured as cmos or as open drain using the spi_od bit. if the open drain option is selected (spi_od = 1) then an external pull-up resistor is required on the sdout or sda output pin. the control interface configuration bits are described in table 67. register address bit label default description r20 (14h) control interface 2 spi_od 0 sdout pin configuration (applies to 3-wire and 4-wire mode only) 0 = sdout output is cmos 1 = sdout output is open drain 1 spi_4wire 1 spi control mode select 0 = 3-wire using bidirectional sda 1 = 4-wire using sdout 0 auto_inc 0 enables address auto-increment (applies to 2-wire / i2c mode only) 0 = disabled 1 = enabled table 67 control interface configuration 2-wire (i2c) control mode in 2-wire mode, the WM8948 is a slave device on the control interface; sclk is a clock input, while sda is a bi-directional data pin. to allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8948 transmits logic 1 by tri-stating the sda pin, rather than pulling it high. an external pull-up resistor is required to pull the sda line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 7-bit device id (this is not the same as the 15-bit address of each register in the WM8948). the WM8948 device id is 34h. the lsb of the device id is the read/write bit; this bit is set to logic 1 for ?read? and logic 0 for ?write?.
production data WM8948 w pd, may 2011, rev 4.1 105 the WM8948 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sda while sclk remains high. this indicates that a device id, register address and data will follow. the WM8948 responds to the start condition and shifts in the next eight bits on sda (7-bit device id + read/write bit, msb first). if the device id received matches the device id of the WM8948, then the WM8948 responds by pulling sda low on the next clock pulse (ack). if the device id is not recognised or the r/w bit is ?1? when operating in write only mode, the WM8948 returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM8948, the data transfer continues as described below. the controller indicates the end of data transfer with a low to high transition on sda while sclk remains high. after receiving a complete address and data sequence the WM8948 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes while sclk is high), the device returns to the idle condition. the WM8948 supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single register write operation is illustrated in figure 39. figure 39 control interface 2-wire (i2c) register write the sequence of signals associated with a single register read operation is illustrated in figure 40. figure 40 control interface 2-wire (i2c) register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 68. note that, for multiple write and multiple read operations, the auto-increment option must be enabled. this feature is enabled by default, as noted in table 67.
WM8948 production data w pd, may 2011, rev 4.1 106 terminology description s start condition sr repeated start a acknowledge p stop condition r/w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM8948 [grey field] data flow from WM8948 to bus master table 68 control interface terminology figure 41 single register write to specified address figure 42 single register read from specified address figure 43 multiple register write to specified address using auto-increment figure 44 multiple register read from specified address using auto-increment
production data WM8948 w pd, may 2011, rev 4.1 107 figure 45 multiple register read from last address using auto-increment multiple write and multiple read operations enable the host processor to access sequential blo cks of the data in the WM8948 register map faster than is possible with single register operations. the auto-increment option is enabled when the auto_inc register bit is set. this bit is defined in table 67. auto-increment is disabled by default. 3-wire (spi) control mode the 3-wire control interface uses the cs , sclk and sda pins. in 3-wire control mode, a control word consists of 32 bits. the first bit is the read/write bit (r/w), which is followed by 15 address bits (a14 to a0) that determine which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. in 3-wire mode, every rising edge of sclk clocks in one data bit from the sda pin. the data is latched on the 32 nd falling edge of sclk after 32 bits of data have been clocked into the device. in write operations (r/w=0), all sda bits are driven by the controlling device. in read operations (r/w=1), the sda pin is driven by the controlling device to clock in the register address, after which the WM8948 drives the sda pin to output the applicable data bits. similarly to 2-wire control mode, the WM8948 can be set to transmit a logic 1 by tri-stating the sda pin, rather than pulling it high (spi_od = 1). an external pull-up resistor is required to pull the sda line high so that the logic 1 can be recognised by the master. the 3-wire control mode timing is illustrated in figure 46. figure 46 3-wire serial control interface 4-wire (spi) control mode the 4-wire control interface uses the cs , sclk, sda and sdout pins. the data output pin, sdout, can be configured as cmos or open drain, as described in table 67. in cmos mode, sdout is driven low when not outputting register data bits. in open drain mode, sdout is undriven (high impedance) when not outputting register data bits. in write operations (r/w=0), this mode is the same as 3-wire mode described above.
WM8948 production data w pd, may 2011, rev 4.1 108 in read operations (r/w=1), the sdata pin is ignored following receipt of the valid register address. sdout is driven by the WM8948. the 4-wire control mode timing is illustrated in figure 47 and figure 48. figure 47 4-wire readback (cmos) figure 48 4-wire readback (open drain) power management the WM8948 has two control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to minimise pop or click noise, it is important to enable or disable these functions in the correct order, and to use the signal mute registers as part of a carefully structured control sequence. refer to the ?recommended power up/down sequence? section for more details. the power management control registers are described in table 69. register address bit label default description r2 (02h) power management 1 13 inppgar_ena 0 right input pga enable 0 = disabled 1 = enabled 12 inppgal_ena 0 left input pga enable 0 = disabled 1 = enabled
production data WM8948 w pd, may 2011, rev 4.1 109 register address bit label default description 11 adcr_ena 0 right adc and record filter enable 0 = disabled 1 = enabled adcr_ena must be set to 1 when processing right channel data from the adc or digital microphone. 10 adcl_ena 0 left adc and record filter enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing left channel data from the adc or digital microphone. 4 micb_ena 0 microphone bias enable 0 = disabled 1 = enabled 3 bias_ena 0 master bias enable 0 = disabled 1 = enabled r3 (03h) power management 2 15 outr_ena 0 lineoutr enable 0 = disabled 1 = enabled 14 outl_ena 0 lineoutl enable 0 = disabled 1 = enabled 13 spkr_pga_ ena 0 speaker right pga enable 0 = disabled 1 = enabled 12 spkl_pga_ ena 0 speaker left pga enable 0 = disabled 1 = enabled 11 spkr_spkvdd _ena 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_op_ena. when powering down spkoutr, the spkr_spkvdd_ena bit should be reset first. 10 spkl_spkvdd _ena 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_op_ena. when powering down spkoutl, the spkl_spkvdd_ena bit should be reset first 7 spkr_op_ena 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_spkvdd_ena. w hen powering up spkoutr, the spkr_op_ena bit s hould be enabled first.
WM8948 production data w pd, may 2011, rev 4.1 110 register address bit label default description 6 spkl_op_ena 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_spkvdd_ena. when powering up spkoutl, the spkl_op_ena bit should be enabled first 3 spkr_mix_ ena 0 right speaker output mixer enable 0 = disabled 1 = enabled 2 spkl_mix_ena 0 left speaker output mixer enable 0 = disabled 1 = enabled 1 dacr_ena 0 right dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing right channel data from the dac or digital beep generator. 0 dacl_ena 0 left dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing left channel data from the dac or digital beep generator. table 69 power management control
production data WM8948 w pd, may 2011, rev 4.1 111 thermal shutdown the WM8948 incorporates a temperature sensor which detects when the device temperature is within normal limits. the temperature status can be read at any time from the temp_sts bit, as described in table 70. this bit can be polled at any time, or may output directly on a gpio pin, or may be used to generate interrupt events. the temperature sensor can be configured to shut down the speaker outputs in the event of an overtemperature condition. this is configured using the therr_act register field. register address bit label default description r17 (11h) status flags 15 temp_sts 0 thermal sensor status 0 = normal 1 = overtemperature r42 (2ah) output ctrl 15 therr_act 1 thermal shutdown enable 0 = disabled 1 = enabled when therr_act = 1, then an overtemperature condition will cause the speaker outputs to be disabled. table 70 thermal shutdown control power on reset the WM8948 includes a power-on reset (por) circuit, which is used to reset the digital logic into a default state after power up. the por circuit derives its output from ldovdd and dcvdd. the internal por si gnal is asserted low when either ldovdd or dcvdd are below minimum thresholds. the specific behaviour of the circuit will vary, depending on relative timing of the supply voltages. typical scenarios are illustrated in figure 49 and figure 50. figure 49 power on reset timing ? ldovdd enabled first
WM8948 production data w pd, may 2011, rev 4.1 112 figure 50 power on reset timing - dcvdd enabled first the por si gnal is undefined until ldovdd has exceeded the minimum threshold, v pora once this threshold has been exceeded, por is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. once ldovdd and dcvdd have both reached their respective power on thresholds, por is released high, all registers are in their default state, and writes to the control interface may take place. note that a minimum power-on reset period, t por , applies even if ldovdd and dcvdd have zero rise time. (this specification is guaranteed by design rather than test.) on power down, por is asserted low w hen ldovdd or dcvdd falls below their respective power- down thresholds. typical power-on reset parameters for the WM8948 are defined in table 71. symbol description min typ max unit v pora power-on undefined threshold (ldovdd) 0.5 v v pora_on power-on threshold (ldovdd) 1.15 v v pora_off power-off threshold (ldovdd) 1.12 v v pord_on power-on threshold (dcvdd) 0.57 v v pord_off power-off threshold (dcvdd) 0.56 v t por minimum power-on reset period 10.6 s table 71 typical power-on reset parameters separate power-on reset circuits are also implemented on the dbvdd and s pkvdd domains. these circuits ensure correct device behaviour whenever these supplies are enabled or disabled.
production data WM8948 w pd, may 2011, rev 4.1 113 recommended power up/down sequence in order to minimise output pop and click noise, it is recommended that the WM8948 device is powered up and down using one of the following sequences: power up: action label register [bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) sw_reset r0 ( 00h) [15:0] enable speaker and line discharge bits spkr_disch = 1 spkl_disch = 1 liner_disch = 1 linel_disch = 1 r42 (2ah) [7] r42 (2ah) [6] r42 (2ah) [5] r42 (2ah) [4] enable vmid to speaker and line outputs spkr_vmid_op_ena = 1 spkl_vmid_op_ena = 1 liner_vmid_op_ena = 1 linel_vmid_op_ena = 1 r42 (2ah) [13] r42 (2ah) [12] r42 (2ah) [11] r42 (2ah) [10] enable vmid fast start and start up bias select start-up bias and set vmid soft start for start-up ramp vmid_fast_start = 1 startup_bias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the reference voltage for the ldo then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ldo start-up bias and enable ldo delay 300ms for ldo to settle ldo_ref_sel_fast = 1 ldo_bias_src = 1 ldo_ena = 1 r53 (35h) [14] r53 (35h) [5] r53 (35h) [15] enable vmid buffer and master bias set vmid_sel[1:0] for fast start-up bias_ena = 1 vmid_buf_ena = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] disable speaker and line discharge bits spkp_disch = 0 spkn_disch = 0 liner_disch = 0 linel_disch = 0 r42 (2ah) [6] r42 (2ah) [7] r42 (2ah) [5] r42 (2ah) [4] enable speaker mixer and dac spkr_mix_ena = 1 spkl_mix_ena = 1 dacr_ena = 1 dacl_ena = 1 r3 (03h) [3] r3 (03h) [2] r3 (03h) [1] r3 (03h) [0] enable speaker outputs and speaker pga and lineout output as required outr_ena = 1 outl_ena = 1 spkr_pga_ena = 1 spkl_pga_ena = 1 spkn_op_ena = 1 spkp_op_ena = 1 r3 (03h) [15] r3 (03h) [14] r3 (03h) [13] r3 (03h) [12] r3 (03h) [7] r3 (03h) [6] enable power to speaker drive spkr_spkvdd_ena = 1 spkl_ spkvdd _ena = 1 r3 (03h) [11] r3 (03h) [10] enable vmid delay 150ms to allow vmid to settle vmid_ena = 1 r7 (07h) [4] set ldo for normal operation ldo_ref_sel_fast = 0 ldo_bias_src = 0 r53 (35h) [14] r53 (35h) [5] set vmid for normal operation vmid_fast_start = 0 r7 (07h) [11]
WM8948 production data w pd, may 2011, rev 4.1 114 action label register [bits] startup_bias_ena = 0 r7 (07h) [8] set vmid divider for normal operation vmid_sel = 01 r2 (02h) [1:0] power down: action label register[bits] mute speaker pga and dac spkr_pga_ena = 1 spkl_pga_ena = 1 spkr_vol = 00h spkl_vol = 00h dacr_mute = 1 dacl_mute = 1 dacr_vol = 0 dacl_vol = 0 r3 (03h) [13] r3 (03h) [12] r47 (2fh) [5:0] r48 (30h) [5:0] r24 (18h) [8] r23 (17h) [8] r24 (18h) [7:0] r23 (17h) [7:0] select ldo for fast start-up ldo_ref_sel_fast = 1 ldo_bias_src = 1 r53 (35h) [14] r53 (35h) [5] select vmid for fast start-up vmid_sel = 11 vmid_fast_start =1 bias_src = 1 vmid_ramp = 01 r2 (02h) [1:0] r7 (07h) [11] r7 (07h) [7] r7 (07h) [6:5] disabled vmid delay 500ms for vmid to discharge vmid_ena = 0 r7 (07h) [4] discharge outputs delay 50ms for outputs to discharge spkr_disch = 1 spkl_disch = 1 liner_disch = 1 linel_disch = 1 r42 (2ah) [7] r42 (2ah) [6] r42 (2ah) [5] r42 (2ah) [4] mute outputs liner_mute = 1 linel_mute = 1 spkr_op_mute = 1 spkl_op_mute = 1 r42 (2ah) [9] r42 (2ah) [8] r03 (03h) [9] r03 (03h) [8] disable power to speaker driver (must be done before disabling the speaker outputs) spkr_spkvdd_ena = 1 spkl_spkvdd_ena = 1 r3 (03h) [11] r3 (03h) [10] disable speaker outputs spkn_op_ena = 1 spkp_op_ena = 1 r3 (03h) [7] r3 (03h) [6] reset sw_reset r0 (00h) [15:0] turn off external power supply voltages
production data WM8948 w pd, may 2011, rev 4.1 115 software reset and device id the WM8948 can be reset by writing to register r0. this is a read-only register, and the contents of r0 will not be affected by writing to this register. the device id can be read back from register r0. the chip revision id can be read back from register 1, as described in table 72. register address bit label default description r0 (00h) software reset/chip id 1 15:0 sw_reset [15:0] 6229h writing to this register resets all registers to their default state. reading from this register will indicate device family id 6229h. r1 (01h) revision number 3:0 chip_rev [3:0] reading from this register will indicate the revision id. table 72 chip reset and id
WM8948 production data w pd, may 2011, rev 4.1 116 register map reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r0 (0h) software reset/chip id 1 sw_reset[15:0] 6229h r1 (1h) chip id 2 0 0 0 0 0 0 0 0 0 0 0 0 chip_rev[3:0] 0000h r2 (2h) power management 1 0 0 inppg ar_en a inppg al_en a adcr _ena adcl_ ena 0 0 dmic_ ena 0 0 micb_ ena bias_ ena vmid_ buf_e na vmid_sel[1:0] 0000h r3 (3h) power management 2 outr _ena outl_ ena spkr_ pga_e na spkl_ pga_e na spkr_ spkv dd_e na spkl_ spkv dd_e na spkr_ op_m ute spkl_ op_m ute spkr_ op_e na spkl_ op_e na spkr_ mix_m ute spkl_ mix_m ute spkr_ mix_e na spkl_ mix_e na dacr _ena dacl_ ena 0330h r4 (4h) audio interface dacdata_pu ll[1:0] frame_pull[ 1:0] bclk_pull[1: 0] adcr _src adcl_ src dacr _src dacl_ src bclk_ inv lrclk _inv wl[1:0] fmt[1:0] 028ah r5 (5h) companding control 0 0 0 0 0 0 0 0 0 0 loop back 0 dac_ comp dac_ comp mode adc_ comp adc_ comp mode 0000h r6 (6h) clock gen control osc_ clk_e na mclk_pull[1: 0] clko ut_se l clkout_div[1 :0] syscl k_ena syscl k_src sysclk_div[2:0] toclk _ena bclk_div[2:0] mstr 0106h r7 (7h) additional control 0 0 0 0 vmid_ fast_ start vmid_ ref_s el vmid_ ctrl start up_bi as_en a bias_ src vmid_ramp[1: 0] vmid_ ena sr[3:0] 000dh r8 (8h) fll control 1 0 0 0 fll_clk_ref _div[1:0] fll_outdiv[2:0] fll_ctrl_rate[2:0] fll_fratio[2:0] fll_f rac fll_e na 0102h r9 (9h) fll control 2 fll_k[15:0] 3127h r10 (ah) fll control 3 0 fll_n[9:0] 0 fll_gain[3:0] 0104h r11 (bh) gpio config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mode _gpio 0000h r12 (ch) gpio1 control gp1_d ir gp1_pull[1:0] gp1_i nt_m ode 0 gp1_p ol 0 0 0 0 gp1_l vl 0 gp1_fn[3:0] 8000h r13 (dh) gpio2 control gp2_d ir gp2_pull[1:0] gp2_i nt_m ode 0 gp2_p ol 0 0 0 0 gp2_l vl 0 gp2_fn[3:0] 8000h r14 (eh) gpio3 control gp3_d ir gp3_pull[1:0] gp3_i nt_m ode 0 gp3_p ol 0 0 0 0 gp3_l vl 0 gp3_fn[3:0] c000h r15 (fh) gpio4 control gp4_d ir gp4_pull[1:0] gp4_i nt_m ode 0 gp4_p ol 0 0 0 0 gp4_l vl 0 gp4_fn[3:0] 8000h r16 (10h) system interrupts temp_ int gp4_i nt gp3_i nt gp2_i nt gp1_i nt tchd ata_i nt tchp d_int auxa dc_in t 0 0 0 0 0 0 0 ldo_u v_int 0000h r17 (11h) status flags temp_ sts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ldo_u v_sts 0000h r18 (12h) irq config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 im_ir q 0001h r19 (13h) system interrupts mask im_te mp_in t im_gp 4_int im_gp 3_int im_gp 2_int im_gp 1_int im_tc hdat a_int im_tc hpd_i nt im_au xadc_ int 0 0 0 0 0 0 0 im_ld o_uv_ int 0000h r20 (14h) control interface 0 0 0 0 0 0 0 0 0 0 0 0 0 spi_o d spi_4 wire auto_ inc 0002h r21 (15h) dac control 1 0 0 0 0 0 0 0 dac_ mute all 0 0 0 dac_a utom ute 0 0 dacr _dati nv dacl_ datin v 0110h r22 (16h) dac control 2 0 0 0 0 0 0 0 0 0 0 0 dac_v ol_ra mp 0 0 0 dac_s b_flt 0010h
production data WM8948 w pd, may 2011, rev 4.1 117 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r23 (17h) left dac digital vol 0 0 0 dac_v u 0 0 0 dacl_ mute dacl_vol[7:0] 00c0h r24 (18h) right dac digital vol 0 0 0 dac_v u 0 0 0 dacr _mut e dacr_vol[7:0] 00c0h r25 (19h) adc control 1 0 0 0 0 0 0 0 adc_ mute all 0 0 0 0 0 0 adcr _dati nv adcl_ datin v 0100h r26 (1ah) adc control 2 0 0 0 0 0 0 0 0 0 0 0 0 0 adc_hpf_cu t[1:0] adc_ hpf 0000h r27 (1bh) left adc digital vol 0 0 0 adc_v u 0 0 0 adcl_ mute adcl_vol[7:0] 00c0h r28 (1ch) right adc digital vol 0 0 0 adc_v u 0 0 0 adcr _mut e adcr_vol[7:0] 00c0h r29 (1dh) drc control 1 0 0 0 0 0 0 0 drc_ ng_e na drc_ ena 0 0 0 1 drc_ qr drc_ antic lip 1 000fh r30 (1eh) drc control 2 0 0 0 drc_ng_mingain[3:0] 0 0 0 1 drc_mingain[2:0] drc_maxgai n[1:0] 0c25h r31 (1fh) drc control 3 0 0 0 0 0 0 1 1 drc_atk[3:0] drc_dcy[3:0] 0342h r32 (20h) drc control 4 0 0 0 drc_knee2_ip[4:0] drc_knee_ip[5:0] 0 0 0000h r33 (21h) drc control 5 0 0 drc_ knee2 _op_e na drc_knee2_op[4:0] drc_knee_op[4:0] drc_hi_comp[2:0] 0003h r34 (22h) drc control 6 0 0 0 0 0 0 0 0 0 0 0 0 drc_qr_thr[ 1:0] drc_qr_dcy[ 1:0] 0000h r35 (23h) drc control 7 0 0 0 0 0 0 drc_ng_exp[ 1:0] drc_lo_comp[2:0] drc_init[4:0] 0000h r36 (24h) drc status drc_gain[15:0] 0000h r37 (25h) beep control 1 0 0 0 0 0 0 0 0 0 beep_gain[3:0] beep_rate[1: 0] beep_ ena 0002h r38 (26h) video buffer 0 0 0 0 0 0 0 0 vb_en a vb_qb oost vb_ga in vb_disoff[2:0] vb_pd vb_cl amp 001ch r39 (27h) input ctrl 0 0 0 0 0 0 0 aux2_ audio aux1_ audio micb_ lvl micrn _to_n _pga r micln _to_n _pgal p_pgar_sel[ 1:0] p_pgal_sel[1 :0] 0035h r40 (28h) left inp pga gain ctrl 0 0 0 0 0 0 0 pga_v u pgal_ zc pgal_ mute pgal_vol[5:0] 0050h r41 (29h) right inp pga gain ctrl 0 0 0 0 0 0 0 pga_v u pgar _zc pgar _mut e pgar_vol[5:0] 0050h r42 (2ah) output ctrl ther r_act 0 spkr_ vmid_ op_e na spkl_ vmid_ op_e na liner _vmid _op_e na linel_ vmid_ op_e na liner _mut e linel_ mute spkr_ disch spkl_ disch liner _disc h linel_ disch 0 0 spk_v roi line_ vroi 8300h r43 (2bh) spk mixer control1 0 0 0 0 0 0 0 aux1_ to_sp kl pgal_ to_sp kl bypl_ to_p gal mdac l_to_ pgal mdac r_to_ pgal dacl_ to_p gal dacr _to_p gal aux2_ to_p gal aux1_ to_p gal 0000h r44 (2ch) spk mixer control2 0 0 0 0 0 0 0 aux1_ to_sp kr pgar _to_s pkr bypr_ to_p gar mdac l_to_ pgar mdac r_to_ pgar dacl_ to_p gar dacr _to_p gar aux2_ to_p gar aux1_ to_p gar 0000h r45 (2dh) spk mixer control3 0 0 0 0 0 0 0 aux1_ to_sp kl_at ten pgal_ to_sp kl_at ten bypl_ to_p gal_a tten 0 0 dacl_ to_p gal_a tten dacr _to_p gal_a tten aux2_ to_p gal_a tten aux1_ to_p gal_a tten 0000h r46 (2eh) spk mixer control4 0 0 0 0 0 0 0 aux1_ to_sp kr_at pgar _to_s pkr_a bypr_ to_p gar_ 0 0 dacl_ to_p gar_ dacr _to_p gar_ aux2_ to_p gar_ aux1_ to_p gar_ 0000h
WM8948 production data w pd, may 2011, rev 4.1 118 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default ten tten atten atten atten atten atten r47 (2fh) left spk volume ctrl 0 0 0 0 0 0 0 spk_v u spkl_ zc spkl_ pga_ mute spkl_vol[5:0] 0079h r48 (30h) right spk volume ctrl 0 0 0 0 0 0 0 spk_v u spkr_ zc spkr_ pga_ mute spkr_vol[5:0] 0079h r49 (31h) line l mixer control 1 0 0 0 0 0 0 0 0 0 bypl_ to_o utl mdac l_to_ outl mdac r_to_ outl dacl_ to_o utl dacr _to_o utl aux2_ to_o utl aux1_ to_o utl 0000h r50 (32h) line r mixer control 1 0 0 0 0 0 0 0 0 0 bypr_ to_o utr mdac l_to_ outr mdac r_to_ outr dacl_ to_o utr dacr _to_o utr aux2_ to_o utr aux1_ to_o utr 0000h r51 (33h) line l mixer control 2 0 0 0 0 0 0 0 0 0 bypl_ to_o utl_a tten 0 0 dacl_ to_o utl_a tten dacr _to_o utl_a tten aux2_ to_o utl_a tten aux1_ to_o utl_a tten 0000h r52 (34h) line r mixer control 2 0 0 0 0 0 0 0 0 0 bypr_ to_o utr_a tten 0 0 dacl_ to_o utr_a tten dacr _to_o utr_a tten aux2_ to_o utr_a tten aux1_ to_o utr_a tten 0000h r53 (35h) ldo ldo_e na ldo_r ef_se l_fas t ldo_r ef_se l ldo_ opflt 0 0 0 0 0 0 ldo_b ias_s rc ldo_vsel[4:0] 0007h r54 (36h) bandgap bg_e na 0 0 0 0 0 0 0 0 0 0 bg_vsel[4:0] 000ah r55 (37h) touch control 1 tch_e na tch_c vt_en a 0 0 0 tch_z _ena tch_y _ena tch_x _ena tch_delay[2:0] tch_rate[4:0] 0000h r56 (38h) touch control 2 0 0 0 0 tch_p donl y 0 0 tch_i sel 0 0 0 0 tch_rpu[3:0] 0007h r57 (39h) touch data x tch_p d1 0 0 0 tch_x[11:0] 0000h r58 (3ah) touch data y tch_p d2 0 0 0 tch_y[11:0] 0000h r59 (3bh) touch data z tch_p d3 0 0 0 tch_z[11:0] 0000h r60 (3ch) auxadc data 0 0 aux_data_s rc[1:0] aux_data[11:0] 0000h r61 (3dh) auxadc control aux_e na aux_c vt_en a 0 0 0 0 0 0 0 0 0 aux_rate[4:0] 0000h r62 (3eh) auxadc source 0 0 0 0 0 0 0 aux_b att_s el 0 0 0 0 0 0 aux_a ux2_s el aux_a ux1_s el 0000h r63 (3fh) auxadc config 0 0 0 0 0 0 aux_a ux1_f iltb aux_b att_s cale 0 0 0 0 0 0 aux_a ux2_r ef aux_a ux1_r ef 0100h r64 (40h) se config selection 0 0 0 0 0 0 0 0 0 0 0 0 se_config[3:0] 0000h r65 (41h) se1_lhpf_config 0 0 0 0 0 0 0 0 0 0 se1_l hpf_r _sign se1_l hpf_l _sign 0 0 se1_l hpf_r _ena se1_l hpf_l _ena 0000h r66 (42h) se1_lhpf_l se1_lhpf_l[15:0] 0000h r67 (43h) se1_lhpf_r se1_lhpf_r[15:0] 0000h r68 (44h) se1_3d_config 0 0 0 se1_3 d_mo no 0 0 se1_3 d_r_s ign se1_3 d_l_si gn se1_3 d_lhp f_r_e na se1_3 d_lhp f_l_e na se1_3 d_r_l hpf_s ign se1_3 d_l_l hpf_s ign 0 0 se1_3 d_r_e na se1_3 d_l_e na 0000h r69 (45h) se1_3d_l 0 0 se1_3d_l_delay[2:0] se1_3d_l_cutoff[2: se1_3d_l_cgain[3:0] se1_3d_l_fgain[3:0] 0408h
production data WM8948 w pd, may 2011, rev 4.1 119 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default 0] r70 (46h) se1_3d_r 0 0 se1_3d_r_delay[2:0] se1_3d_r_cutoff[2: 0] se1_3d_r_cgain[3:0] se1_3d_r_fgain[3:0] 0408h r71 (47h) se1_notch_confi g 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se1_n otch _r_en a se1_n otch _l_en a 0000h r72 (48h) se1_notch_a10 se1_notch_a10[15:0] 0000h r73 (49h) se1_notch_a11 se1_notch_a11[15:0] 0000h r74 (4ah) se1_notch_a20 se1_notch_a20[15:0] 0000h r75 (4bh) se1_notch_a21 se1_notch_a21[15:0] 0000h r76 (4ch) se1_notch_a30 se1_notch_a30[15:0] 0000h r77 (4dh) se1_notch_a31 se1_notch_a31[15:0] 0000h r78 (4eh) se1_notch_a40 se1_notch_a40[15:0] 0000h r79 (4fh) se1_notch_a41 se1_notch_a41[15:0] 0000h r80 (50h) se1_notch_a50 se1_notch_a50[15:0] 0000h r81 (51h) se1_notch_a51 se1_notch_a51[15:0] 0000h r82 (52h) se1_notch_m10 se1_notch_m10[15:0] 0000h r83 (53h) se1_notch_m11 se1_notch_m11[15:0] 1000h r84 (54h) se1_notch_m20 se1_notch_m20[15:0] 0000h r85 (55h) se1_notch_m21 se1_notch_m21[15:0] 1000h r86 (56h) se1_notch_m30 se1_notch_m30[15:0] 0000h r87 (57h) se1_notch_m31 se1_notch_m31[15:0] 1000h r88 (58h) se1_notch_m40 se1_notch_m40[15:0] 0000h r89 (59h) se1_notch_m41 se1_notch_m41[15:0] 1000h r90 (5ah) se1_notch_m50 se1_notch_m50[15:0] 0000h r91 (5bh) se1_notch_m51 se1_notch_m51[15:0] 1000h r92 (5ch) se1_df1_config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se1_d f1_r_ ena se1_d f1_l_ ena 0000h r93 (5dh) se1_df1_l0 se1_df1_l0[15:0] 1000h r94 (5eh) se1_df1_l1 se1_df1_l1[15:0] 0000h r95 (5fh) se1_df1_l2 se1_df1_l2[15:0] 0000h r96 (60h) se1_df1_r0 se1_df1_r0[15:0] 1000h r97 (61h) se1_df1_r1 se1_df1_r1[15:0] 0000h r98 (62h) se1_df1_r2 se1_df1_r2[15:0] 0000h r100 (64h) se2_retune_con fig 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se2_r etun e_r_e na se2_r etun e_l_e na 0000h r101 (65h) se2_retune_c0 se2_retune_c0[15:0] 1000h r102 (66h) se2_retune_c1 se2_retune_c1[15:0] 0000h r103 (67h) se2_retune_c2 se2_retune_c2[15:0] 0000h r104 (68h) se2_retune_c3 se2_retune_c3[15:0] 0000h r105 (69h) se2_retune_c4 se2_retune_c4[15:0] 0000h r106 (6ah) se2_retune_c5 se2_retune_c5[15:0] 0000h r107 (6bh) se2_retune_c6 se2_retune_c6[15:0] 0000h r108 (6ch) se2_retune_c7 se2_retune_c7[15:0] 0000h r109 (6dh) se2_retune_c8 se2_retune_c8[15:0] 0000h r110 (6eh) se2_retune_c9 se2_retune_c9[15:0] 0000h r111 (6fh) se2_retune_c10 se2_retune_c10[15:0] 0000h r112 (70h) se2_retune_c11 se2_retune_c11[15:0] 0000h r113 (71h) se2_retune_c12 se2_retune_c12[15:0] 0000h r114 (72h) se2_retune_c13 se2_retune_c13[15:0] 0000h r115 (73h) se2_retune_c14 se2_retune_c14[15:0] 0000h
WM8948 production data w pd, may 2011, rev 4.1 120 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r116 (74h) se2_retune_c15 se2_retune_c15[15:0] 0000h r117 (75h) se2_retune_c16 se2_retune_c16[15:0] 0000h r118 (76h) se2_retune_c17 se2_retune_c17[15:0] 0000h r119 (77h) se2_retune_c18 se2_retune_c18[15:0] 0000h r120 (78h) se2_retune_c19 se2_retune_c19[15:0] 0000h r121 (79h) se2_retune_c20 se2_retune_c20[15:0] 0000h r122 (7ah) se2_retune_c21 se2_retune_c21[15:0] 0000h r123 (7bh) se2_retune_c22 se2_retune_c22[15:0] 0000h r124 (7ch) se2_retune_c23 se2_retune_c23[15:0] 0000h r125 (7dh) se2_retune_c24 se2_retune_c24[15:0] 0000h r126 (7eh) se2_retune_c25 se2_retune_c25[15:0] 0000h r127 (7fh) se2_retune_c26 se2_retune_c26[15:0] 0000h r128 (80h) se2_retune_c27 se2_retune_c27[15:0] 0000h r129 (81h) se2_retune_c28 se2_retune_c28[15:0] 0000h r130 (82h) se2_retune_c29 se2_retune_c29[15:0] 0000h r131 (83h) se2_retune_c30 se2_retune_c30[15:0] 0000h r132 (84h) se2_retune_c31 se2_retune_c31[15:0] 0000h r133 (85h) se2_5beq_config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se2_5 beq_l _ena 0000h r134 (86h) se2_5beq_l10g 0 0 0 se2_5beq_l1g[4:0] 0 0 0 se2_5beq_l0g[4:0] 0c0ch r135 (87h) se2_5beq_l32g 0 0 0 se2_5beq_l3g[4:0] 0 0 0 se2_5beq_l2g[4:0] 0c0ch r136 (88h) se2_5beq_l4g 0 0 0 0 0 0 0 0 0 0 0 se2_5beq_l4g[4:0] 000ch r137 (89h) se2_5beq_l0p se2_5beq_l0p[15:0] 00d8h r138 (8ah) se2_5beq_l0a se2_5beq_l0a[15:0] 0fcah r139 (8bh) se2_5beq_l0b se2_5beq_l0b[15:0] 0400h r140 (8ch) se2_5beq_l1p se2_5beq_l1p[15:0] 01c5h r141 (8dh) se2_5beq_l1a se2_5beq_l1a[15:0] 1eb5h r142 (8eh) se2_5beq_l1b se2_5beq_l1b[15:0] f145h r143 (8fh) se2_5beq_l1c se2_5beq_l1c[15:0] 0b75h r144 (90h) se2_5beq_l2p se2_5beq_l2p[15:0] 0558h r145 (91h) se2_5beq_l2a se2_5beq_l2a[15:0] 1c58h r146 (92h) se2_5beq_l2b se2_5beq_l2b[15:0] f373h r147 (93h) se2_5beq_l2c se2_5beq_l2c[15:0] 0a54h r148 (94h) se2_5beq_l3p se2_5beq_l3p[15:0] 1103h r149 (95h) se2_5beq_l3a se2_5beq_l3a[15:0] 168eh r150 (96h) se2_5beq_l3b se2_5beq_l3b[15:0] f829h r151 (97h) se2_5beq_l3c se2_5beq_l3c[15:0] 07adh r152 (98h) se2_5beq_l4p se2_5beq_l4p[15:0] 4000h r153 (99h) se2_5beq_l4a se2_5beq_l4a[15:0] 0564h r154 (9ah) se2_5beq_l4b se2_5beq_l4b[15:0] 0559h r155 (9bh) se2_5beq_r10g 0 0 0 se2_5beq_r1g[4:0] 0 0 0 se2_5beq_r0g[4:0] 0c0ch r156 (9ch) se2_5beq_r32g 0 0 0 se2_5beq_r3g[4:0] 0 0 0 se2_5beq_r2g[4:0] 0c0ch r157 (9dh) se2_5beq_r4g 0 0 0 0 0 0 0 0 0 0 0 se2_5beq_r4g[4:0] 000ch r158 (9eh) se2_5beq_r0p se2_5beq_r0p[15:0] 00d8h r159 (9fh) se2_5beq_r0a se2_5beq_r0a[15:0] 0fcah r160 (a0h) se2_5beq_r0b se2_5beq_r0b[15:0] 0400h r161 (a1h) se2_5beq_r1p se2_5beq_r1p[15:0] 01c5h r162 (a2h) se2_5beq_r1a se2_5beq_r1a[15:0] 1eb5h r163 (a3h) se2_5beq_r1b se2_5beq_r1b[15:0] f145h r164 (a4h) se2_5beq_r1c se2_5beq_r1c[15:0] 0b75h r165 (a5h) se2_5beq_r2p se2_5beq_r2p[15:0] 0558h r166 (a6h) se2_5beq_r2a se2_5beq_r2a[15:0] 1c58h r167 (a7h) se2_5beq_r2b se2_5beq_r2b[15:0] f373h
production data WM8948 w pd, may 2011, rev 4.1 121 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r168 (a8h) se2_5beq_r2c se2_5beq_r2c[15:0] 0a54h r169 (a9h) se2_5beq_r3p se2_5beq_r3p[15:0] 1103h r170 (aah) se2_5beq_r3a se2_5beq_r3a[15:0] 168eh r171 (abh) se2_5beq_r3b se2_5beq_r3b[15:0] f829h r172 (ach) se2_5beq_r3c se2_5beq_r3c[15:0] 07adh r173 (adh) se2_5beq_r4p se2_5beq_r4p[15:0] 4000h r174 (aeh) se2_5beq_r4a se2_5beq_r4a[15:0] 0564h r175 (afh) se2_5beq_r4b se2_5beq_r4b[15:0] 0559h
WM8948 production data w pd, may 2011, rev 4.1 122 register bits by address the complete register map is shown below. the detailed description can be found in the relevant text of the device description. register address bit label default description refer to r0 (00h) software reset/chip id 1 15:0 sw_reset [15:0] 0110_0010 _0010_100 1 writing to this register resets all registers to their default state. reading from this register will indicate device family id 6229h. register 00h software reset/chip id 1 register address bit label default description refer to r1 (01h) chip id 2 3:0 chip_rev[3:0] 0000 reading from this register will indicate the revision id. register 01h chip id 2 register address bit label default description refer to r2 (02h) power management 1 13 inppgar_en a 0 right input pga enable 0 = disabled 1 = enabled 12 inppgal_ena 0 left input pga enable 0 = disabled 1 = enabled 11 adcr_ena 0 right adc enable 0 = disabled 1 = enabled adcr_ena must be set to 1 when processing right channel data from the adc or digital microphone. 10 adcl_ena 0 left adc enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing left channel data from the adc or digital microphone. 7 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0, the digital microphone clock (dmicclk) is held low. 4 micb_ena 0 microphone bias enable 0 = disabled 1 = enabled 3 bias_ena 0 master bias enable 0 = disabled 1 = enabled 2 vmid_buf_en a 0 vmid buffer enable. (the buffered vmid may be applied to disabled input and output pins.) 0 = disabled 1 = enabled 1:0 vmid_sel[1:0] 00 vmid divider enable and select
production data WM8948 w pd, may 2011, rev 4.1 123 register address bit label default description refer to 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) register 02h power management 1 register address bit label default description refer to r3 (03h) power management 2 15 outr_ena 0 lineoutr enable 0 = disabled 1 = enabled 14 outl_ena 0 lineoutl enable 0 = disabled 1 = enabled 13 spkr_pga_e na 0 speaker right pga enable 0 = disabled 1 = enabled 12 spkl_pga_e na 0 speaker left pga enable 0 = disabled 1 = enabled 11 spkr_spkvd d_ena 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_op_ena. when powering down spkoutr, the spkr_spkvdd_ena bit should be reset first. 10 spkl_spkvd d_ena 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_op_ena. when powering down spkoutl, the spkl_spkvdd_ena bit s hould be reset first 9 spkr_op_mu te 1 spkoutr output mute 0 = disable mute 1 = enable mute 8 spkl_op_mu te 1 spkoutl output mute 0 = disable mute 1 = enable mute 7 spkr_op_en a 0 spkoutr enable 0 = disabled 1 = enabled note that spkoutr is also controlled by spkr_spkvdd_ena. when powering up spkoutr, the spkr_op_ena bit should be enabled first. 6 spkl_op_en a 0 spkoutl enable 0 = disabled 1 = enabled note that spkoutl is also controlled by spkl_spkvdd_ena. w hen powering up spkoutl, the spkl_op_ena bit should be enabled first 5 spkr_mix_m ute 1 right speaker pga mixer mute 0 = disable mute 1 = enable mute
WM8948 production data w pd, may 2011, rev 4.1 124 register address bit label default description refer to 4 spkl_mix_mu te 1 left speaker pga mixer mute 0 = disable mute 1 = enable mute 3 spkr_mix_en a 0 right speaker output mixer enable 0 = disabled 1 = enabled 2 spkl_mix_en a 0 left speaker output mixer enable 0 = disabled 1 = enabled 1 dacr_ena 0 right dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing right channel data from the dac or digital beep generator. 0 dacl_ena 0 left dac enable 0 = disabled 1 = enabled dacr_ena must be set to 1 when processing left channel data from the dac or digital beep generator. register 03h power management 2 register address bit label default description refer to r4 (04h) audio interface 15:14 dacdata_pu ll[1:0] 00 dacdat pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 frame_pull [1:0] 00 lrclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 bclk_pull [1:0] 00 bclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 9 adcr_src 1 right digital audio interface source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 8 adcl_src 0 left digital audio interface source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 7 dacr_src 1 right dac data source select 0 = right dac outputs left interface data 1 = right dac outputs right interface data 6 dacl_src 0 left dac data source select 0 = left dac outputs left interface data 1 = left dac outputs right interface data 5 bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted
production data WM8948 w pd, may 2011, rev 4.1 125 register address bit label default description refer to 4 lrclk_inv 0 lrclk polarity / dsp mode a-b select. right, left and i2s modes ? lrclk polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrclk rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrclk rising edge (mode b) 3:2 wl[1:0] 10 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits note - see ?companding? for the selection of 8-bit mode. 1:0 fmt[1:0] 10 digital audio interface format 00 = reserved 01 = left justified 10 = i2s format 11 = dsp/pcm mode register 04h audio interface register address bit label default description refer to r5 (05h) companding control 5 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input). 3 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 2 dac_compm ode 0 dac companding mode 0 = -law 1 = a-law 1 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 0 adc_compm ode 0 adc companding mode 0 = -law 1 = a-law register 05h companding control
WM8948 production data w pd, may 2011, rev 4.1 126 register address bit label default description refer to r6 (06h) clock gen control 15 osc_clk_en a 0 oscillator enable 0 = disabled 1 = enabled this needs to be set when doing auxadc measurements, or when a timeout clock is required for pga zero cross or gpio input detection 14:13 mclk_pull [1:0] 00 mclk pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 clkout_sel 0 clkout source select 0 = sysclk 1 = fll or mclk (set by sysclk_src register) 11:10 clkout_div [1:0] 00 clkout clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 sysclk_ena 0 sysclk enable 0 = disabled 1 = enabled 8 sysclk_src 1 sysclk source select 0 = mclk 1 = fll output 7:5 sysclk_div [2:0] 000 sysclk clock divider (sets the scaling for either the mclk or fll clock output, depending on sysclk_src) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 toclk_ena 0 toclk enabled (enables timeout clock for gpio level detection, amu, and pga zero cross timeout) 0 = disabled 1 = enabled 3:1 bclk_div[2:0] 011 bclk frequency (master mode) 000 = sysclk 001 = sysclk / 2 010 = sysclk / 4 011 = sysclk / 8 100 = sysclk / 16 101 = sysclk / 32 110 = reserved 111 = reserved 0 mstr 0 digital audio interface mode select 0 = slave mode 1 = master mode register 06h clock gen control
production data WM8948 w pd, may 2011, rev 4.1 127 register address bit label default description refer to r7 (07h) additional control 11 vmid_fast_ start 0 vmid (fast-start) enable 0 = disabled 1 = enabled 10 vmid_ref_ sel 0 vmid source select 0 = ldo supply (ldovdd) 1 = ldo output (ldovout) 9 vmid_ctrl 0 vmid ratio control sets the ratio of vmid to the source selected by vmid_ref_sel 0 = 5/11 1 = 1/2 8 startup_ bias_ena 0 start-up bias enable 0 = disabled 1 = enabled 7 bias_src 0 bias source select 0 = normal bias 1 = start-up bias 6:5 vmid_ramp [1:0] 00 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = normal soft start 11 = slow soft start 4 vmid_ena 0 vmid enable 0 = disabled 1 = enabled 3:0 sr[3:0] 1101 audio sample rate select 0011 = 8khz 0100 = 11.025khz 0101 = 12khz 0111 = 16khz 1000 = 22.05khz 1001 = 24khz 1011 = 32khz 1100 = 44.1khz 1101 = 48khz register 07h additional control
WM8948 production data w pd, may 2011, rev 4.1 128 register address bit label default description refer to r8 (08h) fll control 1 12:11 fll_clk_ref _div[1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 10:8 fll_outdiv [2:0] 001 fout clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 (fout = fvco / fll_outdiv) 7:5 fll_ctrl_ra te[2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3 011 = fvco / 4 100 = fvco / 5 101 = fvco / 6 110 = fvco / 7 111 = fvco / 8 recommended that this register is not changed from default. 4:2 fll_fratio [2:0] 000 fvco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 000 recommended for fref > 1mhz 100 recommended for fref < 16khz 011 recommended for all other cases 1 fll_frac 1 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non-integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled register 08h fll control 1
production data WM8948 w pd, may 2011, rev 4.1 129 register address bit label default description refer to r9 (09h) fll control 2 15:0 fll_k[15:0] 0011_0001 _0010_011 1 fractional multiply for fref (msb = 0.5) register 09h fll control 2 register address bit label default description refer to r10 (0ah) fll control 3 14:5 fll_n[9:0] 00_0000_1 000 integer multiply for fref (lsb = 1) 3:0 fll_gain[3:0] 0100 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that this register is not changed from default. register 0ah fll control 3 register address bit label default description refer to r11 (0bh) gpio config 0 mode_gpio 0 cifmode/gpio3 pin configuration 0 = pin configured as cifmode 1 = pin configured as gpio3 note - when this bit is set to 1, it is latched and cannot be reset until power-off or software reset. register 0bh gpio config
WM8948 production data w pd, may 2011, rev 4.1 130 register address bit label default description refer to r12 (0ch) gpio1 control 15 gp1_dir 1 gpio1 pin direction 0 = output 1 = input 14:13 gp1_pull[1:0] 00 gpio1 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp1_int_mo de 0 gpio1 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp1_pol=0) or falling edge triggered (if gp1_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp1_pol 0 gpio1 polarity select 0 = non-inverted 1 = inverted 5 gp1_lvl 0 gpio1 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp1_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp1_fn[3:0] 0000 gpio1 pin function 0000 = logic level input 0001 = edge detection input 0010 = clkout output 0011 = interrupt (irq) output 0100 = pen down output 0101 = touch panel measurement complete output 0110 = aux adc measurement complete output 0111 = temperature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved register 0ch gpio1 control
production data WM8948 w pd, may 2011, rev 4.1 131 register address bit label default description refer to r13 (0dh) gpio2 control 15 gp2_dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2_pull[1:0] 00 gpio2 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp2_int_mo de 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2_pol=0) or falling edge triggered (if gp2_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp2_pol 0 gpio2 polarity select 0 = non-inverted 1 = inverted 5 gp2_lvl 0 gpio2 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp2_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp2_fn[3:0] 0000 gpio2 pin function 0000 = logic level input 0001 = edge detection input 0010 = clkout output 0011 = interrupt (irq) output 0100 = pen down output 0101 = touch panel measurement complete output 0110 = aux adc measurement complete output 0111 = temperature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved register 0dh gpio2 control
WM8948 production data w pd, may 2011, rev 4.1 132 register address bit label default description refer to r14 (0eh) gpio3 control 15 gp3_dir 1 gpio3 pin direction 0 = output 1 = input 14:13 gp3_pull[1:0] 10 gpio3 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp3_int_mo de 0 gpio3 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp3_pol=0) or falling edge triggered (if gp3_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp3_pol 0 gpio3 polarity select 0 = non-inverted 1 = inverted 5 gp3_lvl 0 gpio3 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp3_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp3_fn[3:0] 0000 gpio3 pin function 0000 = logic level input 0001 = edge detection input 0010 = clkout output 0011 = interrupt (irq) output 0100 = pen down output 0101 = touch panel measurement complete output 0110 = aux adc measurement complete output 0111 = temperature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved register 0eh gpio3 control
production data WM8948 w pd, may 2011, rev 4.1 133 register address bit label default description refer to r15 (0fh) gpio4 control 15 gp4_dir 1 gpio4 pin direction 0 = output 1 = input 14:13 gp4_pull[1:0] 00 gpio4 pull-up / pull-down enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 gp4_int_mo de 0 gpio4 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp4_pol=0) or falling edge triggered (if gp4_pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp4_pol 0 gpio4 polarity select 0 = non-inverted 1 = inverted 5 gp4_lvl 0 gpio4 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp4_pol is set, the register contains the opposite logic level to the external pin. 3:0 gp4_fn[3:0] 0000 gpio4 pin function 0000 = logic level input 0001 = edge detection input 0010 = clkout output 0011 = interrupt (irq) output 0100 = pen down output 0101 = touch panel measurement complete output 0110 = aux adc measurement complete output 0111 = temperature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved register 0fh gpio4 control
WM8948 production data w pd, may 2011, rev 4.1 134 register address bit label default description refer to r16 (10h) system interrupts 15 temp_int 0 thermal interrupt status 0 = thermal interrupt not set 1 = thermal interrupt set this bit is latched when set; it is cleared when the register is read. 14 gp4_int 0 gpio4 interrupt status 0 = gpio4 interrupt not set 1 = gpio4 interrupt set this bit is latched when set; it is cleared when the register is read. 13 gp3_int 0 gpio3 interrupt status 0 = gpio3 interrupt not set 1 = gpio3 interrupt set this bit is latched when set; it is cleared when the register is read. 12 gp2_int 0 gpio2 interrupt status 0 = gpio2 interrupt not set 1 = gpio2 interrupt set this bit is latched when set; it is cleared when the register is read. 11 gp1_int 0 gpio1 interrupt status 0 = gpio1 interrupt not set 1 = gpio1 interrupt set this bit is latched when set; it is cleared when the register is read. 10 tchdata_int 0 touch panel data ready interrupt 0 = touch panel data ready interrupt not set 1 = touch panel data ready interrupt set this bit is latched when set; it is cleared when the register is read. 9 tchpd_int 0 touch panel pen down interrupt 0 = touch panel pen down interrupt not set 1 = touch panel pen down interrupt set this bit is latched when set; it is cleared when the register is read. 8 auxadc_int 0 auxadc data ready interrupt 0 = auxadc data ready interrupt not set 1 = auxadc data ready interrupt set this bit is latched when set; it is cleared when the register is read. 0 ldo_uv_int 0 ldo undervoltage interrupt 0 = ldo undervoltage interrupt not set 1 = ldo undervoltage interrupt set this bit is latched when set; it is cleared when the register is read. register 10h system interrupts
production data WM8948 w pd, may 2011, rev 4.1 135 register address bit label default description refer to r17 (11h) status flags 15 temp_sts 0 thermal sensor status 0 = normal 1 = overtemperature 0 ldo_uv_sts 0 ldo undervoltage status 0 = normal 1 = undervoltage register 11h status flags register address bit label default description refer to r18 (12h) irq config 0 im_irq 1 irq (gpio output) mask 0 = normal 1 = irq output is masked register 12h irq config register address bit label default description refer to r19 (13h) system interrupts mask 15 im_temp_int 0 interrupt mask for thermal status 0 = not masked 1 = masked 14 im_gp4_int 0 interrupt mask for gpio4 0 = not masked 1 = masked 13 im_gp3_int 0 interrupt mask for gpio3 0 = not masked 1 = masked 12 im_gp2_int 0 interrupt mask for gpio2 0 = not masked 1 = masked 11 im_gp1_int 0 interrupt mask for gpio1 0 = not masked 1 = masked 10 im_tchdata_ int 0 interrupt mask for touch panel data ready status 0 = not masked 1 = masked 9 im_tchpd_in t 0 interrupt mask for touch panel pen down status 0 = not masked 1 = masked 8 im_auxadc_i nt 0 interrupt mask for auxadc data ready status 0 = not masked 1 = masked 0 im_ldo_uv_i nt 0 interrupt mask for ldo undervoltage status 0 = not masked 1 = masked register 13h system interrupts mask
WM8948 production data w pd, may 2011, rev 4.1 136 register address bit label default description refer to r20 (14h) control interface 2 spi_od 0 sdout pin configuration (applies to 4-wire mode only) 0 = sdout output is cmos 1 = sdout output is open drain 1 spi_4wire 1 spi control mode select 0 = 3-wire using bidirectional sda 1 = 4-wire using sdout 0 auto_inc 0 enables address auto-increment (applies to 2-wire / i2c mode only) 0 = disabled 1 = enabled register 14h control interface register address bit label default description refer to r21 (15h) dac control 1 8 dac_muteal l 1 dac digital mute for all channels: 0 = disable mute 1 = enable mute on all channels 4 dac_automu te 1 dac auto-mute control 0 = disabled 1 = enabled 1 dacr_datin v 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted 0 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted register 15h dac control 1 register address bit label default description refer to r22 (16h) dac control 2 4 dac_vol_ra mp 1 dac volume ramp control 0 = disabled 1 = enabled 0 dac_sb_flt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode register 16h dac control 2
production data WM8948 w pd, may 2011, rev 4.1 137 register address bit label default description refer to r23 (17h) left dac digital vol 12 dac_vu 0 dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 8 dacl_mute 0 left dac digital mute 0 = disable mute 1 = enable mute 7:0 dacl_vol [7:0] 1100_0000 left dac digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db register 17h left dac digital vol register address bit label default description refer to r24 (18h) right dac digital vol 12 dac_vu 0 dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 8 dacr_mute 0 right dac digital mute 0 = disable mute 1 = enable mute 7:0 dacr_vol [7:0] 1100_0000 right dac volume control 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db register 18h right dac digital vol
WM8948 production data w pd, may 2011, rev 4.1 138 register address bit label default description refer to r25 (19h) adc control 1 8 adc_muteal l 1 adc digital mute for all channels 0 = disable mute 1 = enable mute on all channels 1 adcr_datin v 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted 0 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted register 19h adc control 1 register address bit label default description refer to r26 (1ah) adc control 2 2:1 adc_hpf_cu t[1:0] 00 high pass filter configuration. 00 = 1st order hpf (fc=4hz at fs=48khz) 01 = 2nd order hpf (fc=122hz at fs=48khz) 10 = 2nd order hpf (fc=153hz at fs=48khz) 11 = 2nd order hpf (fc=196hz at fs=48khz) table 11 0 adc_hpf 0 adc digital high pass filter enable 0 = disabled 1 = enabled register 1ah adc control 2 register address bit label default description refer to r27 (1bh) left adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 8 adcl_mute 0 left adc digital mute 0 = disable mute 1 = enable mute 7:0 adcl_vol [7:0] 1100_0000 left adc digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db register 1bh left adc digital vol
production data WM8948 w pd, may 2011, rev 4.1 139 register address bit label default description refer to r28 (1ch) right adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 8 adcr_mute 0 right adc digital mute 0 = disable mute 1 = enable mute 7:0 adcr_vol [7:0] 1100_0000 right adc digital volume 0000_0000 = mute 0000_0001 = -71.625db 0000_0010 = -71.250db ? 1100_0000 = 0db ... 1111_1111 = +23.625db register 1ch right adc digital vol register address bit label default description refer to r29 (1dh) drc control 1 8 drc_ng_ena 0 drc noise gate enable 0 = disabled 1 = enabled 7 drc_ena 0 drc enable 0 = disabled 1 = enabled 2 drc_qr 1 drc quick-release enable 0 = disabled 1 = enabled 1 drc_anticli p 1 drc anti-clip enable 0 = disabled 1 = enabled register 1dh drc control 1
WM8948 production data w pd, may 2011, rev 4.1 140 register address bit label default description refer to r30 (1eh) drc control 2 12:9 drc_ng_min gain[3:0] 0110 minimum gain the drc can use to attenuate audio signals when the noise gate is active. 0000 = -36db 0001 = -30db 0010 = -24db 0011 = -18db 0100 = -12db 0101 = -6db 0110 = 0db 0111 = 6db 1000 = 12db 1001 = 18db 1010 = 24db 1011 = 30db 1100 = 36db 1101 to 1111 = reserved 4:2 drc_mingain [2:0] 001 minimum gain the drc can use to attenuate audio signals 000 = 0db 001 = -12db (default) 010 = -18db 011 = -24db 100 = -36db 101 = reserved 11x = reserved 1:0 drc_maxgai n[1:0] 01 maximum gain the drc can use to boost audio signals (db) 00 = 12db 01 = 18db 10 = 24db 11 = 36db register 1eh drc control 2
production data WM8948 w pd, may 2011, rev 4.1 141 register address bit label default description refer to r31 (1fh) drc control 3 7:4 drc_atk[3:0] 0100 gain attack rate (seconds/6db) 0000 = reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = reserved 3:0 drc_dcy[3:0] 0010 gain decay rate (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved register 1fh drc control 3 register address bit label default description refer to r32 (20h) drc control 4 12:8 drc_knee2_i p[4:0] 0_0000 input signal level at the noise gate threshold ?knee2?. 00000 = -36db 00001 = -37.5db 00010 = -39db ? (-1.5db steps) 11110 = -81db 11111 = -82.5db only applicable when drc_ng_ena = 1. 7:2 drc_knee_ip [5:0] 00_0000 input signal level at the compressor ?knee1?. 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 = reserved 11111x = reserved register 20h drc control 4
WM8948 production data w pd, may 2011, rev 4.1 142 register address bit label default description refer to r33 (21h) drc control 5 13 drc_knee2_ op_ena 0 drc_knee2_op enable 0 = disabled 1 = enabled 12:8 drc_knee2_ op[4:0] 0_0000 output signal at the noise gate threshold ?knee2?. 00000 = -30db 00001 = -31.5db 00010 = -33db ? (-1.5db steps) 11110 = -75db 11111 = -76.5db only applicable when drc_knee2_op_ena = 1. 7:3 drc_knee_o p[4:0] 0_0000 output signal at the compressor ?knee1?. 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved 2:0 drc_hi_com p[2:0] 011 compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = reserved 111 = reserved register 21h drc control 5 register address bit label default description refer to r34 (22h) drc control 6 3:2 drc_qr_thr [1:0] 00 drc quick-release threshold (crest factor in db) 00 = 12db 01 = 18db 10 = 24db 11 = 30db 1:0 drc_qr_dcy [1:0] 00 drc quick-release decay rate (seconds/6db) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved register 22h drc control 6
production data WM8948 w pd, may 2011, rev 4.1 143 register address bit label default description refer to r35 (23h) drc control 7 9:8 drc_ng_exp [1:0] 00 noise gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 7:5 drc_lo_com p[2:0] 000 compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved 4:0 drc_init 00000 initial value at drc startup 00000 = 0db 00001 = -3.75db ? (-3.75db steps) 11111 = -116.25db register 23h drc control 7 register address bit label default description refer to r36 (24h) drc status 15:0 drc_gain [15:0] 0000_0000 _0000_000 0 drc gain value. this is the drc gain, expressed as a voltage multiplier. fixed point coding, msb = 64. the first 7 bits are the integer portion; the remaining bits are the fractional part. register 24h drc status register address bit label default description refer to r37 (25h) beep control 1 6:3 beep_gain [3:0] 0000 digital beep volume control 0000 = mute 0001 = -83db 0010 = -77db ? (6db steps) 1111 = +1db 2:1 beep_rate [1:0] 01 beep waveform control 00 = reserved 01 = 1khz 10 = 2khz 11 = 4khz 0 beep_ena 0 digital beep enable 0 = disabled 1 = enabled note that the dac and associated signal path needs to be enabled when using the digital beep. register 25h beep control 1
WM8948 production data w pd, may 2011, rev 4.1 144 register address bit label default description refer to r38 (26h) video buffer 7 vb_ena 0 video buffer enable 0 = disabled 1 = enabled 6 vb_qboost 0 video buffer filter q-boost control 0 = disabled 1 = enabled 5 vb_gain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = 6db (=12db unloaded) 4:2 vb_disoff [2:0] 111 video buffer dc offset control 000 = reserved 001 = 40mv offset 010 = reserved 011 = 20mv offset 100 = reserved 101 = reserved 110 = reserved 111 = 0mv offset note ? the specified offset applies to the 0db gain setting (vb_gain=0). when 6db gain is selected, the dc offset is doubled. 1 vb_pd 0 video buffer pull-down 0 = pull-down disabled 1 = pull-down enabled 0 vb_clamp 0 enable the clamp between the video input and ground 0 = no clamp 1 = video buffer input is clamped to ground register 26h video buffer register address bit label default description refer to r39 (27h) input ctrl 8 aux2_audio 0 aux2 pin configuration 0 = non-audio signal 1 = ac-coupled audio signal 7 aux1_audio 0 aux1 pin configuration 0 = non-audio signal 1 = ac-coupled audio signal 6 micb_lvl 0 microphone bias voltage control 0 = 0.9 x ldovout 1 = 0.65 x ldovout 5 micrn_to_n _pgar 1 right input pga inverting input select 0 = connected to vmid 1 = connected to in2r 4 micln_to_n_ pgal 1 left input pga inverting input select 0 = connected to vmid 1 = connected to in2l 3:2 p_pgar_sel [1:0] 01 right input pga non-inverting input select 00 = connected to in2r 01 = connected to in1r 10 = connected to aux2 11 = reserved
production data WM8948 w pd, may 2011, rev 4.1 145 register address bit label default description refer to 1:0 p_pgal_sel [1:0] 01 left input pga non-inverting input select 00 = connected to in2l 01 = connected to in1l 10 = connected to aux1 11 = reserved register 27h input ctrl register address bit label default description refer to r40 (28h) left inp pga gain ctrl 8 pga_vu 0 input pga volume update writing a 1 to this bit will cause the left and right input pga volumes to be updated simultaneously. 7 pgal_zc 0 left input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 pgal_mute 1 left input pga mute 0 = disable mute 1 = enable mute 5:0 pgal_vol [5:0] 01_0000 left input pga volume 00_0000 = -12db 00_0001 = -11.25db ? 01_0000 = 0db ... 11_1111 = +35.25 register 28h left inp pga gain ctrl register address bit label default description refer to r41 (29h) right inp pga gain ctrl 8 pga_vu 0 input pga volume update writing a 1 to this bit will cause the left and right input pga volumes to be updated simultaneously. 7 pgar_zc 0 right input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 pgar_mute 1 right input pga mute 0 = disable mute 1 = enable mute 5:0 pgar_vol [5:0] 01_0000 right input pga volume 00_0000 = -12db 00_0001 = -11.25db ? 01_0000 = 0db ... 11_1111 = +35.25 register 29h right inp pga gain ctrl
WM8948 production data w pd, may 2011, rev 4.1 146 register address bit label default description refer to r42 (2ah) output ctrl 15 therr_act 1 thermal shutdown enable 0 = disabled 1 = enabled when therr_act = 1, then an overtemperature condition will cause the speaker outputs to be disabled. 13 spkr_vmid_ op_ena 0 buffered vmid to spkoutr enable 0 = disabled 1 = enabled 12 spkl_vmid_o p_ena 0 buffered vmid to spkoutl enable 0 = disabled 1 = enabled 11 liner_vmid_ op_ena 0 buffered vmid to lineoutr enable 0 = disabled 1 = enabled 10 linel_vmid_ op_ena 0 buffered vmid to lineoutl enable 0 = disabled 1 = enabled 9 liner_mute 1 lineoutr output mute 0 = disable mute 1 = enable mute 8 linel_mute 1 lineoutl output mute 0 = disable mute 1 = enable mute 7 spkr_disch 0 discharges spkoutr output via approx 4k resistor 0 = not active 1 = actively discharging spkoutr 6 spkl_disch 0 discharges spkoutl output via approx 4k resistor 0 = not active 1 = actively discharging spkoutl 5 liner_disch 0 discharges lineoutr output via approx 4k resistor 0 = not active 1 = actively discharging lineoutr 4 linel_disch 0 discharges lineoutl output via approx 4k resistor 0 = not active 1 = actively discharging lineoutl 1 spk_vroi 0 buffered vref to spkoutl / spkoutr resistance (disabled outputs) 0 = approx 20k 1 = approx 1k 0 line_vroi 0 buffered vref to lineoutl / lineoutr resistance (disabled outputs) 0 = approx 20k 1 = approx 1k register 2ah output ctrl
production data WM8948 w pd, may 2011, rev 4.1 147 register address bit label default description refer to r43 (2bh) spk mixer control1 8 aux1_to_sp kl 0 aux1 audio input to left speaker output select 0 = disabled 1 = enabled 7 pgal_to_sp kl 0 left speaker pga mixer to left speaker output select 0 = disabled 1 = enabled 6 bypl_to_pg al 0 left input pga (adc bypass) to left speaker pga mixer select 0 = disabled 1 = enabled 5 mdacl_to_p gal 0 inverted left dac to left speaker pga mixer select 0 = disabled 1 = enabled 4 mdacr_to_p gal 0 inverted right dac to left speaker pga mixer select 0 = disabled 1 = enabled 3 dacl_to_pg al 0 left dac to left speaker pga mixer select 0 = disabled 1 = enabled 2 dacr_to_pg al 0 right dac to left speaker pga mixer select 0 = disabled 1 = enabled 1 aux2_to_pg al 0 aux2 audio input to left speaker pga mixer select 0 = disabled 1 = enabled 0 aux1_to_pg al 0 aux1 audio input to left speaker pga mixer select 0 = disabled 1 = enabled register 2bh spk mixer control1 register address bit label default description refer to r44 (2ch) spk mixer control2 8 aux1_to_sp kr 0 aux1 audio input to right speaker output select 0 = disabled 1 = enabled 7 pgar_to_sp kr 0 right speaker pga mixer to right speaker output select 0 = disabled 1 = enabled 6 bypr_to_pg ar 0 right input pga (adc bypass) to right speaker pga mixer select 0 = disabled 1 = enabled 5 mdacl_to_p gar 0 inverted left dac to right speaker pga mixer select 0 = disabled 1 = enabled 4 mdacr_to_p gar 0 inverted right dac to right speaker pga mixer select 0 = disabled 1 = enabled 3 dacl_to_pg ar 0 left dac to right speaker pga mixer select 0 = disabled
WM8948 production data w pd, may 2011, rev 4.1 148 register address bit label default description refer to 1 = enabled 2 dacr_to_pg ar 0 right dac to right speaker pga mixer select 0 = disabled 1 = enabled 1 aux2_to_pg ar 0 aux2 audio input to right speaker pga mixer select 0 = disabled 1 = enabled 0 aux1_to_pg ar 0 aux1 audio input to right speaker pga mixer select 0 = disabled 1 = enabled register 2ch spk mixer control2 register address bit label default description refer to r45 (2dh) spk mixer control3 8 aux1_to_sp kl_atten 0 aux1 audio input to left speaker output attenuation 0 = 0db 1 = -6db attenuation 7 pgal_to_sp kl_atten 0 left speaker pga mixer to left speaker output attenuation 0 = 0db 1 = -6db attenuation 6 bypl_to_pg al_atten 0 left input pga (adc bypass) to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_pg al_atten 0 left dac to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_pg al_atten 0 right dac to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_pg al_atten 0 aux2 audio input to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_pg al_atten 0 aux1 audio input to left speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation register 2dh spk mixer control3
production data WM8948 w pd, may 2011, rev 4.1 149 register address bit label default description refer to r46 (2eh) spk mixer control4 8 aux1_to_sp kr_atten 0 aux1 audio input to right speaker output attenuation 0 = 0db 1 = -6db attenuation 7 pgar_to_sp kr_atten 0 right speaker pga mixer to right speaker output attenuation 0 = 0db 1 = -6db attenuation 6 bypr_to_pg ar_atten 0 right input pga (adc bypass) to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_pg ar_atten 0 left dac to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_pg ar_atten 0 right dac to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_pg ar_atten 0 aux2 audio input to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_pg ar_atten 0 aux1 audio input to right speaker pga mixer attenuation 0 = 0db 1 = -6db attenuation register 2eh spk mixer control4 register address bit label default description refer to r47 (2fh) left spk volume ctrl 8 spk_vu 0 speaker pga volume update writing a 1 to this bit will cause the left and right speaker pga volumes to be updated simultaneously. 7 spkl_zc 0 left speaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 spkl_pga_m ute 1 left speaker pga mute 0 = disable mute 1 = enable mute 5:0 spkl_vol [5:0] 11_1001 left speaker pga volume 00_0000 = -57db gain 00_0001 = -56db ? 11_1001 = 0db ... 11_1111 = +6db register 2fh left spk volume ctrl
WM8948 production data w pd, may 2011, rev 4.1 150 register address bit label default description refer to r48 (30h) right spk volume ctrl 8 spk_vu 0 speaker pga volume update writing a 1 to this bit will cause the left and right speaker pga volumes to be updated simultaneously. 7 spkr_zc 0 right speaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 spkr_pga_m ute 1 right speaker pga mute 0 = disable mute 1 = enable mute 5:0 spkr_vol [5:0] 11_1001 right speaker pga volume 00_0000 = -57db gain 00_0001 = -56db ? 11_1001 = 0db ... 11_1111 = +6db register 30h right spk volume ctrl register address bit label default description refer to r49 (31h) line l mixer control 1 6 bypl_to_ou tl 0 left input pga (adc bypass) to left output mixer select 0 = disabled 1 = enabled 5 mdacl_to_o utl 0 inverted left dac to left output mixer select 0 = disabled 1 = enabled 4 mdacr_to_o utl 0 inverted right dac to left output mixer select 0 = disabled 1 = enabled 3 dacl_to_ou tl 0 left dac to left output mixer select 0 = disabled 1 = enabled 2 dacr_to_ou tl 0 right dac to left output mixer select 0 = disabled 1 = enabled 1 aux2_to_ou tl 0 aux2 audio input to left output mixer select 0 = disabled 1 = enabled 0 aux1_to_ou tl 0 aux1 audio input to left output mixer select 0 = disabled 1 = enabled register 31h line l mixer control 1
production data WM8948 w pd, may 2011, rev 4.1 151 register address bit label default description refer to r50 (32h) line r mixer control 1 6 bypr_to_ou tr 0 right input pga (adc bypass) to right output mixer select 0 = disabled 1 = enabled 5 mdacl_to_o utr 0 inverted left dac to right output mixer select 0 = disabled 1 = enabled 4 mdacr_to_o utr 0 inverted right dac to right output mixer select 0 = disabled 1 = enabled 3 dacl_to_ou tr 0 left dac to right output mixer select 0 = disabled 1 = enabled 2 dacr_to_ou tr 0 right dac to right output mixer select 0 = disabled 1 = enabled 1 aux2_to_ou tr 0 aux2 audio input to right output mixer select 0 = disabled 1 = enabled 0 aux1_to_ou tr 0 aux1 audio input to right output mixer select 0 = disabled 1 = enabled register 32h line r mixer control 1 register address bit label default description refer to r51 (33h) line l mixer control 2 6 bypl_to_ou tl_atten 0 left input pga (adc bypass) to left output mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_ou tl_atten 0 left dac to left output mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_ou tl_atten 0 right dac to left output mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_ou tl_atten 0 aux2 audio input to left output mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_ou tl_atten 0 aux1 audio input to left output mixer attenuation 0 = 0db 1 = -6db attenuation register 33h line l mixer control 2
WM8948 production data w pd, may 2011, rev 4.1 152 register address bit label default description refer to r52 (34h) line r mixer control 2 6 bypr_to_ou tr_atten 0 right input pga (adc bypass) to right output mixer attenuation 0 = 0db 1 = -6db attenuation 3 dacl_to_ou tr_atten 0 left dac to right output mixer attenuation 0 = 0db 1 = -6db attenuation 2 dacr_to_ou tr_atten 0 right dac to right output mixer attenuation 0 = 0db 1 = -6db attenuation 1 aux2_to_ou tr_atten 0 aux2 audio input to right output mixer attenuation 0 = 0db 1 = -6db attenuation 0 aux1_to_ou tr_atten 0 aux1 audio input to right output mixer attenuation 0 = 0db 1 = -6db attenuation register 34h line r mixer control 2 register address bit label default description refer to r53 (35h) ldo 15 ldo_ena 0 ldo enable 0 = disabled 1 = enabled 14 ldo_ref_se l_fast 0 ldo voltage reference select 0 = vmid (normal) 1 = vmid (fast start) this field is only effective when ldo_ref_sel = 0 13 ldo_ref_se l 0 ldo voltage reference select 0 = vmid 1 = bandgap 12 ldo_opflt 0 ldo output float 0 = disabled (output discharged when disabled) 1 = enabled (output floats when disabled) 5 ldo_bias_sr c 0 ldo bias source select 0 = master bias 1 = start-up bias 4:0 ldo_vsel [4:0] 0_0111 ldo voltage select (sets the ldo output as a ratio of the selected voltage reference. the voltage reference is set by ldo_ref_sel.) 00111 = vref x 1.97 (default) register 35h ldo
production data WM8948 w pd, may 2011, rev 4.1 153 register address bit label default description refer to r54 (36h) bandgap 15 bg_ena 0 bandgap reference control 0 = disabled 1 = enabled 4:0 bg_vsel[4:0] 0_1010 bandgap voltage select (sets the bandgap voltage) 00000 = 1.200v ? 26.7mv steps 01010 = 1.467v (default) ? 01111 = 1.600v 10000 to 11111 = reserved (see table 39 for values) register 36h bandgap register address bit label default description refer to r55 (37h) touch control 1 15 tch_ena 0 touch panel enable 0 = disabled 1 = enabled 14 tch_cvt_en a 0 touch panel conversion enable 0 = disabled 1 = enabled in automatic mode, conversions are enabled by setting this bit. in manual mode (tch_rate = 0), setting this bit will initiate a set of conversion; the bit is reset automatically. 10 tch_z_ena 0 enables z-axis touch panel measurements. 0 = disabled 1 = enabled 9 tch_y_ena 0 enables y-axis touch panel measurements 0 = disabled 1 = enabled 8 tch_x_ena 0 enables x-axis touch panel measurements 0 = disabled 1 = enabled 7:5 tch_delay [2:0] 000 settling time between x, y and z measurements. (nominal timing only; typically +/-20% of quoted values.) 000 = 30us 001 = 60us 010 = 120us 011 = 240us 100 = 480us 101 = 960us 110 = 1920us 111 = 3840us 4:0 tch_rate [4:0] 0_0000 touch panel rate 0_0000 = manual conversion 0_0001 = 16khz 0_0010 = 32khz ?(16khz steps) 1_1111 = 496khz register 37h touch control 1
WM8948 production data w pd, may 2011, rev 4.1 154 register address bit label default description refer to r56 (38h) touch control 2 11 tch_pdonly 0 select automatic conversions only when pen down is detected. (no effect on manual conversion.) 0 = normal 1 = pen-down only 8 tch_isel 0 pressure measurement current select 0 = 230ua 1 = 460ua 3:0 tch_rpu[3:0] 0111 pen-down sensitivity (pull-up resistor) 0000 = 64k (most sensitive) 0001 = 64k / 2 0010 = 64k / 3 0011 = 64k / 4 ?. 1111 = 64k / 16 (least sensitive) register 38h touch control 2 register address bit label default description refer to r57 (39h) touch data x 15 tch_pd1 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_x[11:0] 0000_0000 _0000 touch panel x-axis data register 39h touch data x register address bit label default description refer to r58 (3ah) touch data y 15 tch_pd2 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_y[11:0] 0000_0000 _0000 touch panel y-axis data register 3ah touch data y register address bit label default description refer to r59 (3bh) touch data z 15 tch_pd3 0 pen down status (indicates if the pen down was detected prior to the tp measurement) 0 = pen down not detected 1 = pen down detected 11:0 tch_z[11:0] 0000_0000 _0000 touch panel z-axis data register 3bh touch data z
production data WM8948 w pd, may 2011, rev 4.1 155 register address bit label default description refer to r60 (3ch) auxadc data 13:12 aux_data_s rc[1:0] 00 auxadc data source 00 = no measurement 01 = aux1 10 = aux2 11 = spkvdd 11:0 aux_data [11:0] 0000_0000 _0000 auxadc data (12 bit unsigned data) register 3ch auxadc data register address bit label default description refer to r61 (3dh) auxadc control 15 aux_ena 0 auxadc enable 0 = disabled 1 = enabled 14 aux_cvt_en a 0 auxadc conversion enable 0 = disabled 1 = enabled in automatic mode, conversions are enabled by setting this bit. in manual mode (aux_rate = 0), setting this bit will initiate a conversion; the bit is reset automatically. 4:0 aux_rate [4:0] 0_0000 auxadc conversion rate 0_0000 = manual conversion 0_0001 = 16hz 0_0010 = 32hz ?(16hz steps) 1_1111 = 496hz register 3dh auxadc control register address bit label default description refer to r62 (3eh) auxadc source 8 aux_batt_s el 0 auxadc battery (spkvdd) input select 0 = disable battery (spkvdd) measurement 1 = enable battery (spkvdd) measurement 1 aux_aux2_s el 0 auxadc aux2 input select 0 = disable aux2 measurement 1 = enable aux2 measurement 0 aux_aux1_s el 0 auxadc aux1 input select 0 = disable aux1 measurement 1 = enable aux1 measurement register 3eh auxadc source
WM8948 production data w pd, may 2011, rev 4.1 156 register address bit label default description refer to r63 (3fh) auxadc config 9 aux_aux1_fi ltb 0 auxadc battery (spkvdd) measurement filter control 0 = disabled 1 = enabled when aux_aux1_filtb is set, the battery (spkvdd) measurement point is connected to the aux1 pin, allowing an external capacitor to be used to filter noise. 8 aux_batt_s cale 1 auxadc battery (spkvdd) measurement divider control 0 = 0.45 x spkvdd (note that 0.45 x 3.3v = 1.485v) 1 = 0.41 x spkvdd (note that 0.41 x 3.6v = 1.476v) 1 aux_aux2_r ef 0 auxadc aux2 reference select 0 = ldovdd/2 1 = 1.5v (nominal) bandgap 0 aux_aux1_r ef 0 auxadc aux1 reference select 0 = ldovdd/2 1 = 1.5v (nominal) bandgap register 3fh auxadc config register address bit label default description refer to r64 (40h) se config selection 3:0 se_config [3:0] 0000 dsp configuration mode select 0000 = record mode 0001 = playback mode 0010 = reserved 0011 = reserved register 40h se config selection register address bit label default description refer to r65 (41h) se1_lhpf_ config 5 se1_lhpf_r_ sign 0 se1_lhpf_r_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 4 se1_lhpf_l_ sign 0 se1_lhpf_l_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 1 se1_lhpf_r_ ena 0 se1 right channel low-pass / high-pass filter enable 0 = disabled 1 = enabled 0 se1_lhpf_l_ ena 0 se1 left channel low-pass / high-pass filter enable 0 = disabled 1 = enabled register 41h se1_lhpf_config
production data WM8948 w pd, may 2011, rev 4.1 157 register address bit label default description refer to r66 (42h) se1_lhpf_ l 15:0 se1_lhpf_l [15:0] 0000_0000 _0000_000 0 se1_lhpf left channel coefficient register 42h se1_lhpf_l register address bit label default description refer to r67 (43h) se1_lhpf_ r 15:0 se1_lhpf_r [15:0] 0000_0000 _0000_000 0 se1_lhpf right channel coefficient register 43h se1_lhpf_r register address bit label default description refer to r68 (44h) se1_3d_c onfig 12 se1_3d_mon o 0 se1_3d_mono : 0 : l, r configs active 1 : l config applied to both l and r 9 se1_3d_r_si gn 0 se1_3d_r_sign 0 : add cross path values 1 : sub cross path values 8 se1_3d_l_si gn 0 se1_3d_l_sign 0 : add cross path values 1 : sub cross path values 7 se1_3d_lhpf _r_ena 0 se1_3d_lhpf_r_ena: 0 : r channel disabled (bypass coeffs applied) 1 : r channel enabled (bank coeffs applied) 6 se1_3d_lhpf _l_ena 0 se1_3d_lhpf_l_ena: 0 : l channel disabled (bypass coeffs applied) 1 : l channel enabled (bank coeffs applied) 5 se1_3d_r_lh pf_sign 0 se1_3d_r_lhpf_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 4 se1_3d_l_lh pf_sign 0 se1_3d_l_lhpf_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 1 se1_3d_r_en a 0 se1 right channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled 0 se1_3d_l_en a 0 se1 left channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled register 44h se1_3d_config
WM8948 production data w pd, may 2011, rev 4.1 158 register address bit label default description refer to r69 (45h) se1_3d_l 13:11 se1_3d_l_de lay[2:0] 000 sets the number of delay samples: 0000 = 0 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 se1_3d_l_cu toff[2:0] 100 cut off frequency 0000 = 50hz 0001 = 100hz 0010 = 200hz 0011 = 400 hz 0100 = 1khz 0101 = 2khz 0110 = 4khz 0111 = 10khz 1000 to 1111 = reserved 7:4 se1_3d_l_cg ain[3:0] 0000 se1 3d left channel cross gain setting 0000 = -12db 0001 = -10.5db ??. 1000= 0db 1001 to 1111 = reserved 3:0 se1_3d_l_fg ain[3:0] 1000 se1 3d left channel forward gain setting 0000 = -12db 0001 = -10.5db ??. 1000= 0db 1001 to 1111 = reserved register 45h se1_3d_l register address bit label default description refer to r70 (46h) se1_3d_r 13:11 se1_3d_r_de lay[2:0] 000 sets the number of delay samples: 0000 = 0 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 se1_3d_r_cu toff[2:0] 100 cut off frequency 0000 = 50hz 0001 = 100hz 0010 = 200hz 0011 = 400 hz 0100 = 1khz 0101 = 2khz 0110 = 4khz 0111 = 10khz 1000 to 1111 = reserved 7:4 se1_3d_r_c gain[3:0] 0000 se1 3d right channel cross gain setting 0000 = -12db 0001 = -10.5db
production data WM8948 w pd, may 2011, rev 4.1 159 register address bit label default description refer to ??. 1000= 0db 1001 to 1111 = reserved 3:0 se1_3d_r_fg ain[3:0] 1000 se1 3d right channel forward gain setting 0000 = -12db 0001 = -10.5db ??. 1000= 0db 1001 to 1111 = reserved register 46h se1_3d_r register address bit label default description refer to r71 (47h) se1_notc h_config 1 se1_notch_ r_ena 0 se1 right channel notch filters enable 0 = disabled 1 = enabled 0 se1_notch_ l_ena 0 se1 left channel notch filters enable 0 = disabled 1 = enabled register 47h se1_notch_config register address bit label default description refer to r72 (48h) se1_notc h_a10 15:0 se1_notch_ a10[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 48h se1_notch_a10 register address bit label default description refer to r73 (49h) se1_notc h_a11 15:0 se1_notch_ a11[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 49h se1_notch_a11 register address bit label default description refer to r74 (4ah) se1_notc h_a20 15:0 se1_notch_ a20[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4ah se1_notch_a20
WM8948 production data w pd, may 2011, rev 4.1 160 register address bit label default description refer to r75 (4bh) se1_notc h_a21 15:0 se1_notch_ a21[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4bh se1_notch_a21 register address bit label default description refer to r76 (4ch) se1_notc h_a30 15:0 se1_notch_ a30[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4ch se1_notch_a30 register address bit label default description refer to r77 (4dh) se1_notc h_a31 15:0 se1_notch_ a31[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4dh se1_notch_a31 register address bit label default description refer to r78 (4eh) se1_notc h_a40 15:0 se1_notch_ a40[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4eh se1_notch_a40 register address bit label default description refer to r79 (4fh) se1_notc h_a41 15:0 se1_notch_ a41[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4fh se1_notch_a41 register address bit label default description refer to r80 (50h) se1_notc h_a50 15:0 se1_notch_ a50[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 50h se1_notch_a50 register address bit label default description refer to r81 (51h) se1_notc h_a51 15:0 se1_notch_ a51[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 51h se1_notch_a51
production data WM8948 w pd, may 2011, rev 4.1 161 register address bit label default description refer to r82 (52h) se1_notc h_m10 15:0 se1_notch_ m10[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 52h se1_notch_m10 register address bit label default description refer to r83 (53h) se1_notc h_m11 15:0 se1_notch_ m11[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 53h se1_notch_m11 register address bit label default description refer to r84 (54h) se1_notc h_m20 15:0 se1_notch_ m20[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 54h se1_notch_m20 register address bit label default description refer to r85 (55h) se1_notc h_m21 15:0 se1_notch_ m21[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 55h se1_notch_m21 register address bit label default description refer to r86 (56h) se1_notc h_m30 15:0 se1_notch_ m30[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 56h se1_notch_m30 register address bit label default description refer to r87 (57h) se1_notc h_m31 15:0 se1_notch_ m31[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 57h se1_notch_m31 register address bit label default description refer to r88 (58h) se1_notc h_m40 15:0 se1_notch_ m40[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 58h se1_notch_m40
WM8948 production data w pd, may 2011, rev 4.1 162 register address bit label default description refer to r89 (59h) se1_notc h_m41 15:0 se1_notch_ m41[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 59h se1_notch_m41 register address bit label default description refer to r90 (5ah) se1_notc h_m50 15:0 se1_notch_ m50[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 5ah se1_notch_m50 register address bit label default description refer to r91 (5bh) se1_notc h_m51 15:0 se1_notch_ m51[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 5bh se1_notch_m51 register address bit label default description refer to r92 (5ch) se1_df1_c onfig 1 se1_df1_r_e na 0 se1 right channel df1 filter enable 0 = disabled 1 = enabled 0 se1_df1_l_e na 0 se1 left channel df1 filter enable 0 = disabled 1 = enabled register 5ch se1_df1_config register address bit label default description refer to r93 (5dh) se1_df1_l 0 15:0 se1_df1_l0 [15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) left channel df1 filter register 5dh se1_df1_l0 register address bit label default description refer to r94 (5eh) se1_df1_l 1 15:0 se1_df1_l1 [15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) left channel df1 filter register 5eh se1_df1_l1
production data WM8948 w pd, may 2011, rev 4.1 163 register address bit label default description refer to r95 (5fh) se1_df1_l 2 15:0 se1_df1_l2 [15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) left channel df1 filter register 5fh se1_df1_l2 register address bit label default description refer to r96 (60h) se1_df1_r 0 15:0 se1_df1_r0 [15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) right channel df1 filter register 60h se1_df1_r0 register address bit label default description refer to r97 (61h) se1_df1_r 1 15:0 se1_df1_r1 [15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) right channel df1 filter register 61h se1_df1_r1 register address bit label default description refer to r98 (62h) se1_df1_r 2 15:0 se1_df1_r2 [15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) right channel df1 filter register 62h se1_df1_r2 register address bit label default description refer to r100 (64h) se2_retu ne_confi g 1 se2_retune _r_ena 0 se2 right channel retune? filter enable 0 = disabled 1 = enabled 0 se2_retune _l_ena 0 se2 left channel retune? filter enable 0 = disabled 1 = enabled register 64h se2_retune_config register address bit label default description refer to r101 (65h) se2_retu ne_c0 15:0 se2_retune _c0[15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 65h se2_retune_c0
WM8948 production data w pd, may 2011, rev 4.1 164 register address bit label default description refer to r102 (66h) se2_retu ne_c1 15:0 se2_retune _c1[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 66h se2_retune_c1 register address bit label default description refer to r103 (67h) se2_retu ne_c2 15:0 se2_retune _c2[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 67h se2_retune_c2 register address bit label default description refer to r104 (68h) se2_retu ne_c3 15:0 se2_retune _c3[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 68h se2_retune_c3 register address bit label default description refer to r105 (69h) se2_retu ne_c4 15:0 se2_retune _c4[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 69h se2_retune_c4 register address bit label default description refer to r106 (6ah) se2_retu ne_c5 15:0 se2_retune _c5[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6ah se2_retune_c5 register address bit label default description refer to r107 (6bh) se2_retu ne_c6 15:0 se2_retune _c6[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6bh se2_retune_c6 register address bit label default description refer to r108 (6ch) se2_retu ne_c7 15:0 se2_retune _c7[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6ch se2_retune_c7
production data WM8948 w pd, may 2011, rev 4.1 165 register address bit label default description refer to r109 (6dh) se2_retu ne_c8 15:0 se2_retune _c8[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6dh se2_retune_c8 register address bit label default description refer to r110 (6eh) se2_retu ne_c9 15:0 se2_retune _c9[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6eh se2_retune_c9 register address bit label default description refer to r111 (6fh) se2_retu ne_c10 15:0 se2_retune _c10[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 6fh se2_retune_c10 register address bit label default description refer to r112 (70h) se2_retu ne_c11 15:0 se2_retune _c11[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 70h se2_retune_c11 register address bit label default description refer to r113 (71h) se2_retu ne_c12 15:0 se2_retune _c12[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 71h se2_retune_c12 register address bit label default description refer to r114 (72h) se2_retu ne_c13 15:0 se2_retune _c13[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 72h se2_retune_c13 register address bit label default description refer to r115 (73h) se2_retu ne_c14 15:0 se2_retune _c14[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 73h se2_retune_c14
WM8948 production data w pd, may 2011, rev 4.1 166 register address bit label default description refer to r116 (74h) se2_retu ne_c15 15:0 se2_retune _c15[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 74h se2_retune_c15 register address bit label default description refer to r117 (75h) se2_retu ne_c16 15:0 se2_retune _c16[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 75h se2_retune_c16 register address bit label default description refer to r118 (76h) se2_retu ne_c17 15:0 se2_retune _c17[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 76h se2_retune_c17 register address bit label default description refer to r119 (77h) se2_retu ne_c18 15:0 se2_retune _c18[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 77h se2_retune_c18 register address bit label default description refer to r120 (78h) se2_retu ne_c19 15:0 se2_retune _c19[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 78h se2_retune_c19 register address bit label default description refer to r121 (79h) se2_retu ne_c20 15:0 se2_retune _c20[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 79h se2_retune_c20 register address bit label default description refer to r122 (7ah) se2_retu ne_c21 15:0 se2_retune _c21[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7ah se2_retune_c21
production data WM8948 w pd, may 2011, rev 4.1 167 register address bit label default description refer to r123 (7bh) se2_retu ne_c22 15:0 se2_retune _c22[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7bh se2_retune_c22 register address bit label default description refer to r124 (7ch) se2_retu ne_c23 15:0 se2_retune _c23[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7ch se2_retune_c23 register address bit label default description refer to r125 (7dh) se2_retu ne_c24 15:0 se2_retune _c24[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7dh se2_retune_c24 register address bit label default description refer to r126 (7eh) se2_retu ne_c25 15:0 se2_retune _c25[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7eh se2_retune_c25 register address bit label default description refer to r127 (7fh) se2_retu ne_c26 15:0 se2_retune _c26[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 7fh se2_retune_c26 register address bit label default description refer to r128 (80h) se2_retu ne_c27 15:0 se2_retune _c27[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 80h se2_retune_c27 register address bit label default description refer to r129 (81h) se2_retu ne_c28 15:0 se2_retune _c28[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 81h se2_retune_c28
WM8948 production data w pd, may 2011, rev 4.1 168 register address bit label default description refer to r130 (82h) se2_retu ne_c29 15:0 se2_retune _c29[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 82h se2_retune_c29 register address bit label default description refer to r131 (83h) se2_retu ne_c30 15:0 se2_retune _c30[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 83h se2_retune_c30 register address bit label default description refer to r132 (84h) se2_retu ne_c31 15:0 se2_retune _c31[15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune? filter register 84h se2_retune_c31 register address bit label default description refer to r133 (85h) se2_5beq_ config 0 se2_5beq_l_ ena 0 se2 left channel 5-band eq enable 0 = disabled 1 = enabled register 85h se2_5beq_config register address bit label default description refer to r134 (86h) se2_5beq_ l10g 12:8 se2_5beq_l1 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db 00100 : -8db 00101 : -7db 00110 : -6db 00111 : -5db 01000 : -4db 01001 : -3db 01010 : -2db 01011 : -1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db
production data WM8948 w pd, may 2011, rev 4.1 169 register address bit label default description refer to 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_l0 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 86h se2_5beq_l10g register address bit label default description refer to r135 (87h) se2_5beq_ l32g 12:8 se2_5beq_l3 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_l2 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 87h se2_5beq_l32g register address bit label default description refer to r136 (88h) se2_5beq_ l4g 4:0 se2_5beq_l4 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 88h se2_5beq_l4g
WM8948 production data w pd, may 2011, rev 4.1 170 register address bit label default description refer to r137 (89h) se2_5beq_ l0p 15:0 se2_5beq_l0 p[15:0] 0000_0000 _1101_100 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 89h se2_5beq_l0p register address bit label default description refer to r138 (8ah) se2_5beq_ l0a 15:0 se2_5beq_l0 a[15:0] 0000_1111 _1100_101 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8ah se2_5beq_l0a register address bit label default description refer to r139 (8bh) se2_5beq_ l0b 15:0 se2_5beq_l0 b[15:0] 0000_0100 _0000_000 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8bh se2_5beq_l0b register address bit label default description refer to r140 (8ch) se2_5beq_ l1p 15:0 se2_5beq_l1 p[15:0] 0000_0001 _1100_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8ch se2_5beq_l1p register address bit label default description refer to r141 (8dh) se2_5beq_ l1a 15:0 se2_5beq_l1 a[15:0] 0001_1110 _1011_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8dh se2_5beq_l1a register address bit label default description refer to r142 (8eh) se2_5beq_ l1b 15:0 se2_5beq_l1 b[15:0] 1111_0001 _0100_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8eh se2_5beq_l1b register address bit label default description refer to r143 (8fh) se2_5beq_ l1c 15:0 se2_5beq_l1 c[15:0] 0000_1011 _0111_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 8fh se2_5beq_l1c
production data WM8948 w pd, may 2011, rev 4.1 171 register address bit label default description refer to r144 (90h) se2_5beq_ l2p 15:0 se2_5beq_l2 p[15:0] 0000_0101 _0101_100 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 90h se2_5beq_l2p register address bit label default description refer to r145 (91h) se2_5beq_ l2a 15:0 se2_5beq_l2 a[15:0] 0001_1100 _0101_100 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 91h se2_5beq_l2a register address bit label default description refer to r146 (92h) se2_5beq_ l2b 15:0 se2_5beq_l2 b[15:0] 1111_0011 _0111_001 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 92h se2_5beq_l2b register address bit label default description refer to r147 (93h) se2_5beq_ l2c 15:0 se2_5beq_l2 c[15:0] 0000_1010 _0101_010 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 93h se2_5beq_l2c register address bit label default description refer to r148 (94h) se2_5beq_ l3p 15:0 se2_5beq_l3 p[15:0] 0001_0001 _0000_001 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 94h se2_5beq_l3p register address bit label default description refer to r149 (95h) se2_5beq_ l3a 15:0 se2_5beq_l3 a[15:0] 0001_0110 _1000_111 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 95h se2_5beq_l3a register address bit label default description refer to r150 (96h) se2_5beq_ l3b 15:0 se2_5beq_l3 b[15:0] 1111_1000 _0010_100 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 96h se2_5beq_l3b
WM8948 production data w pd, may 2011, rev 4.1 172 register address bit label default description refer to r151 (97h) se2_5beq_ l3c 15:0 se2_5beq_l3 c[15:0] 0000_0111 _1010_110 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 97h se2_5beq_l3c register address bit label default description refer to r152 (98h) se2_5beq_ l4p 15:0 se2_5beq_l4 p[15:0] 0100_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 98h se2_5beq_l4p register address bit label default description refer to r153 (99h) se2_5beq_ l4a 15:0 se2_5beq_l4 a[15:0] 0000_0101 _0110_010 0 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 99h se2_5beq_l4a register address bit label default description refer to r154 (9ah) se2_5beq_ l4b 15:0 se2_5beq_l4 b[15:0] 0000_0101 _0101_100 1 filter coefficients for signal enhancement 2 (se2) left channel 5-band eq filter register 9ah se2_5beq_l4b register address bit label default description refer to r155 (9bh) se2_5beq_ r10g 12:8 se2_5beq_r1 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db 00100 : -8db 00101 : -7db 00110 : -6db 00111 : -5db 01000 : -4db 01001 : -3db 01010 : -2db 01011 : -1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db
production data WM8948 w pd, may 2011, rev 4.1 173 register address bit label default description refer to 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_r0 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 9bh se2_5beq_r10g register address bit label default description refer to r156 (9ch) se2_5beq_ r32g 12:8 se2_5beq_r3 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_r2 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 9ch se2_5beq_r32g register address bit label default description refer to r157 (9dh) se2_5beq_ r4g 4:0 se2_5beq_r4 g[4:0] 0_1100 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter gain 00000 : -12db 00001 : -12db 00010 : -10db 00011 : -9db ?. (1db steps) 11000 : 12db 11001 to 11111 : reserved register 9dh se2_5beq_r4g
WM8948 production data w pd, may 2011, rev 4.1 174 register address bit label default description refer to r158 (9eh) se2_5beq_ r0p 15:0 se2_5beq_r0 p[15:0] 0000_0000 _1101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register 9eh se2_5beq_r0p register address bit label default description refer to r159 (9fh) se2_5beq_ r0a 15:0 se2_5beq_r0 a[15:0] 0000_1111 _1100_101 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register 9fh se2_5beq_r0a register address bit label default description refer to r160 (a0h) se2_5beq_ r0b 15:0 se2_5beq_r0 b[15:0] 0000_0100 _0000_000 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a0h se2_5beq_r0b register address bit label default description refer to r161 (a1h) se2_5beq_ r1p 15:0 se2_5beq_r1 p[15:0] 0000_0001 _1100_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a1h se2_5beq_r1p register address bit label default description refer to r162 (a2h) se2_5beq_ r1a 15:0 se2_5beq_r1 a[15:0] 0001_1110 _1011_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a2h se2_5beq_r1a register address bit label default description refer to r163 (a3h) se2_5beq_ r1b 15:0 se2_5beq_r1 b[15:0] 1111_0001 _0100_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a3h se2_5beq_r1b register address bit label default description refer to r164 (a4h) se2_5beq_ r1c 15:0 se2_5beq_r1 c[15:0] 0000_1011 _0111_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a4h se2_5beq_r1c
production data WM8948 w pd, may 2011, rev 4.1 175 register address bit label default description refer to r165 (a5h) se2_5beq_ r2p 15:0 se2_5beq_r2 p[15:0] 0000_0101 _0101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a5h se2_5beq_r2p register address bit label default description refer to r166 (a6h) se2_5beq_ r2a 15:0 se2_5beq_r2 a[15:0] 0001_1100 _0101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a6h se2_5beq_r2a register address bit label default description refer to r167 (a7h) se2_5beq_ r2b 15:0 se2_5beq_r2 b[15:0] 1111_0011 _0111_001 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a7h se2_5beq_r2b register address bit label default description refer to r168 (a8h) se2_5beq_ r2c 15:0 se2_5beq_r2 c[15:0] 0000_1010 _0101_010 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a8h se2_5beq_r2c register address bit label default description refer to r169 (a9h) se2_5beq_ r3p 15:0 se2_5beq_r3 p[15:0] 0001_0001 _0000_001 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register a9h se2_5beq_r3p register address bit label default description refer to r170 (aah) se2_5beq_ r3a 15:0 se2_5beq_r3 a[15:0] 0001_0110 _1000_111 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register aah se2_5beq_r3a register address bit label default description refer to r171 (abh) se2_5beq_ r3b 15:0 se2_5beq_r3 b[15:0] 1111_1000 _0010_100 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register abh se2_5beq_r3b
WM8948 production data w pd, may 2011, rev 4.1 176 register address bit label default description refer to r172 (ach) se2_5beq_ r3c 15:0 se2_5beq_r3 c[15:0] 0000_0111 _1010_110 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register ach se2_5beq_r3c register address bit label default description refer to r173 (adh) se2_5beq_ r4p 15:0 se2_5beq_r4 p[15:0] 0100_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register adh se2_5beq_r4p register address bit label default description refer to r174 (aeh) se2_5beq_ r4a 15:0 se2_5beq_r4 a[15:0] 0000_0101 _0110_010 0 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register aeh se2_5beq_r4a register address bit label default description refer to r175 (afh) se2_5beq_ r4b 15:0 se2_5beq_r4 b[15:0] 0000_0101 _0101_100 1 filter coefficients for signal enhancement 2 (se2) right channel 5-band eq filter register afh se2_5beq_r4b
production data WM8948 w pd, may 2011, rev 4.1 177 digital filter characteristics parameter test conditions min typ max unit adc filter passband +/- 0.1db 0 0.454 fs -6db 0.5fs passband ripple +/- 0.1 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db dac normal filter passband +/- 0.03db 0 0.454 fs -6db 0.5 fs passband ripple 0.454 fs +/- 0.03 db stopband 0.546 fs stopband attenuation f > 0.546 fs -50 db dac sloping stopband filter passband +/- 0.03db 0 0.25 fs +/- 1db 0.25 fs 0.454 fs -6db 0.5 fs passband ripple 0.25 fs +/- 0.03 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs -60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs -85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs -55 db dac filters adc filters mode group delay mode group delay normal 16.5 / fs normal 16.5 / fs sloping stopband 18 / fs terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region note: the group delays are quoted with the dsp se1, se2, and se3 filters disabled. enabling the dsp se1, se2, and se3 filters will increase the group delay
WM8948 production data w pd, may 2011, rev 4.1 178 adc filter response 0 -50 -100 -150 -200 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 figure 51 adc frequency response up to 4 x fs (sample rate, fs = 48khz) 30m 20m 10m 0m -10m -20m -30m -40m 20k 15k 10k 5k 0 figure 52 adc pass band frequency response up to fs/2 (sample rate, fs = 48khz)
production data WM8948 w pd, may 2011, rev 4.1 179 adc highpass filter response 0 -5 -10 -15 -20 0.1 k 10 1 figure 53 adc high pass filter frequency response for the hi-fi mode (sample rate, fs = 48khz) apps0 0 -5 -10 -15 -20 apps1 apps2 apps3 apps4 apps5 apps6 apps7 1k 0.1k 10 figure 54 adc high pass filter frequency response for the application mode (sample rate, fs = 48khz)
WM8948 production data w pd, may 2011, rev 4.1 180 dac filter response 0 -50 -100 -150 -200 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 figure 55 dac frequency response up to 4 x fs (sample rate, fs = 32k to 48khz) 0 -50 -100 -150 -200 90k 80k 70k 60k 50k 40k 30k 20k 10k 0 figure 56 dac frequency response up to 4 x fs (sample rate, fs = 16k to 24khz)
production data WM8948 w pd, may 2011, rev 4.1 181 0 -50 -100 -150 -200 40k 30k 20k 10k 0 figure 57 dac frequency response up to 4 x fs (sample rate, fs = 8k to 12khz) figure 58 dac pass band frequency response up to fs/2 (sample rate, fs = 8k to 12khz, 16k to 24khz, 32k to 48khz) 12k 40m 20m 0m -20m -40m -60m 24k 48k 20k 15k 10k 5k 0
WM8948 production data w pd, may 2011, rev 4.1 182 applications information recommended external components audio input paths the WM8948 provides up to 6 analogue audio inputs (including the auxiliary inputs aux1 and aux2). each of these inputs is referenced to the internal dc reference, vmid. a dc blocking capacitor is required for each input pin used in the target application. the choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin. the circuit is illustrated in figure 59. (note that capacitors are not required on any unused audio input.) figure 59 audio input path dc blocking capacitor when the input impedance is known, and the cut-off frequency is known, then the minimum capacitor value may be derived easily. for practical use, a 1 f capacitance for all audio inputs can be recommended for most cases. tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size. ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must be taken to ensure the desired capacitance is maintained at the ldovout operating voltage. also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. this is particularly problematic for microphone input paths where a large signal gain is required. a single capacitor is required for a line input or single-ended microphone connection. in the case of a differential microphone connection, a dc blocking capacitor is required on both input pins. headphone / line output paths the WM8948 provides four outputs (lineoutl, lineoutr, spkoutl and spkoutr). each of these outputs is referenced to the internal dc reference, vmid. in any case where a line output is used in a single-ended configuration (i.e. referenced to gnd), a dc blocking capacitor is required in order to remove the dc bias. in the case where a pair of line outputs is configured as a btl differential pair, then the dc blocking capacitor should be omitted. the choice of capacitor is determined from the filter that is formed between the capacitor and the load impedance. a 1 f capacitance would be a suitable choice for a line or headphone load. tantalum electrolytic capacitors are again particularly suitable but ceramic equivalents are a cost effective alternative. care must be taken to ensure the desired capacitance is maintained at the appropriate operating voltage.
production data WM8948 w pd, may 2011, rev 4.1 183 figure 60 dc-blocking components for line output figure 61 dc-blocking components for headphone output btl speaker output connection the btl speaker output connection is a differential mode of operation. the loudspeaker may be connected directly across the spkoutl and spkoutr pins. no additional external components are required in this case. power supply decoupling electrical coupling exists particularly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. this effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. the resultant variations (or ?spikes?) in the power supply voltage can cause malfunctions and unintentional behavior in other components. a decoupling (or ?bypass?) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunctions that could otherwise arise. coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. in audio components such as the WM8948, these variations can alter the performance of the signal path, leading to degradation in signal quality. a decoupling (or ?bypass?) capacitor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled. these coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. in the case of systems comprising multiple power supply rails, decoupling should be provided on each rail.
WM8948 production data w pd, may 2011, rev 4.1 184 the recommended power supply decoupling capacitors for WM8948 are listed below in table 73. power supply decoupling capacitor dcvdd, dbvdd, ldovdd, spkvdd 4.7 f ceramic ldovout 2.2 f ceramic vmidc 4.7 f ceramic table 73 power supply decoupling capacitors all decoupling capacitors should be placed as close as possible to the WM8948 device. the connection between gnd, the ldovout decoupling capacitor and the main system ground should be made at a single point as close as possible to the gnd ball of the WM8948. the vmidc capacitor is not, technically, a decoupling capacitor. however, it does serve a similar purpose in filtering noise on the vmid reference. the connection between gnd, the vmid decoupling capacitor and the main system ground should be made at a single point as close as possible to the gnd ball of the WM8948. due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. for most application the use of ceramic capacitors with capacitor dielectric x5r is recommended. microphone bias circuit the WM8948 is designed to interface easily with electret microphones. these may be connected in single-ended or differential configurations. the single-ended method allows greater capability for the connection of multiple audio sources simultaneously, whilst the differential method provides better performance due to its rejection of common-mode noise. in either configuration, the microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones), which can be provided by micbias. this reference is generated by an output-compensated amplifier, which requires an external capacitor in order to guarantee accuracy and stability. the recommended capacitance is 4.7 f, although it may be possible to reduce this to 1 f if the analogue supply (ldovout) is not too noisy. a ceramic type is a suitable choice here, providing that care is taken to choose a component that exhibits this capacitance at the intended micbias voltage. note that the micbias voltage may be adjusted using register control to suit the requirements of the microphone. also note the WM8948 supports a maximum current of 3ma. if more than one microphone is connected to the micbias, then combined current must not exceed 3ma. a current-limiting resistor is also required when using an electret condenser microphone (ecm). the resistance should be chosen according to the minimum operating impedance of the microphone and micbias voltage so that the maximum bias current of the WM8948 is not exceeded. wolfson recommends a 2.2k current limiting resistor as it provides compatibility with a wide range of microphone models. the recommended connections for single-ended and differential microphone modes are illustrated in figure 62 and figure 63.
production data WM8948 w pd, may 2011, rev 4.1 185 figure 62 single-ended microphone connection figure 63 pseudo-differential microphone connection video buffer components external components are required for the video buffer. in a typical application, r load = 75 , r source = 75 , r ref = 187 . see ?video buffer? for details of alternative components under different load impedance conditions. ldovdd vbref video buffer vbin vbout tv in 6db / 12db (unloaded) 0db / 6db (fully loaded) lpf clamp r ref r source r load r ref = 187 ohms r source = 75 ohms r load = 75 ohms figure 64 typical components for video buffer
WM8948 production data w pd, may 2011, rev 4.1 186 recommended external components diagram figure 65 provides a summary of recommended external components for WM8948. note that the actual requirements may differ according to the specific target application. figure 65 WM8948 recommended external components diagram pcb layout considerations poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. all external components should be placed as close to the WM8948 device as possible, with current loop areas kept as small as possible.
production data WM8948 w pd, may 2011, rev 4.1 187 package dimensions b: 36 ball w-csp package 2.960 x 3.060 x 0.7mm body, 0.50 mm ball pitch a1 corner top view e z 0.10 2 x d 5 4 detail 2 detail 2 a a2 2 z 0.10 2 x a1 z bbb z 1 e1 a d1 detail 1 d c b f e e e bottom view 1 654 32 6 g notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. this dimension includes stand-off height ?a1? and backside coating. 3. a1 corner is identified by ink/laser mark on top package. 4. bilateral tolerance zone is applied to each side of the package body. 5. ?e? represents the basic solder ball grid pitch. 6. this drawing is subject to change without notice. 7. follows jedec design guide mo-211-c. a1 0.219 d d1 e e1 e 2.500 bsc 3.060 bsc 0.220 2.500 bsc 0.500 bsc 2.960 bsc dimensions (mm) symbols min nom max note a 0.7 a2 0.361 0.386 0.411 5 f1 0.785 0.615 0.244 0.269 g 0.070 0.035 0.105 h 0.314 bsc f2 0.270 f1 f2 h dm063.a
WM8948 production data w pd, may 2011, rev 4.1 188 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
production data WM8948 w pd, may 2011, rev 4.1 189 revision history date rev description of changes page changed by 08/10/10 4.0 touch pressure current added added comment about adc volume being in digital filter block added comment about dac volume being in digital filter block notch filter plots updated added note about dac_vol_ramp rate r56 tch_isel currents changed from 200ua and 460ua 12 31 49 37 50 95, 155 bc 16/05/11 4.1 added note about ldovdd being enabled before spkvdd for pop-free start-up 8 jj

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